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What do JasperGold, Stratus, and the Rocketick part of Xcelium have in common? Well, they are all Cadence products, of course. But they also all use Verific as parsers for SystemVerilog, Verilog, and VHDL.
Verific got started twenty years ago, Rob Dekker told me. In 1999, he had been working at Exemplar (before it was acquired by Mentor). They were an FPGA synthesis company and Rob was working on their VHDL and Verilog language front-end. He thought a bit about what he was doing and wondered why he was only doing it for one company. There was no reason for every EDA company to develop their own language front-ends—nobody buys your synthesizer because it has a great parser. He figured somebody should write a language front-end for the whole EDA industry.
So he decided to do it himself. When he left Exemplar, he started Verific. The original idea was also to build verification tools, in particular, a low-cost logical equivalence checker. Hence the Verific name that is more like "verification" than "language front-end". Several companies turned out to be interested, so he licensed three or four, which got some money to fund further development. The first companies were:
The Fujitsu product got discontinued, Theseus Logic is no more, but HDL Works and RealIntent are still customers.
The big milestone, though, was when Altera licensed the technology. FPGA companies would turn out to be a sweet spot since they needed parsers but barely differentiated on their software, let alone their parsers. In turn, Xilinx, Lattice, Actel, and Microsemi (some of which have since been acquired, as has Altera) would license the technology. Licensing Altera meant Rob had enough money to hire his first employee, Lawrence Neukom. He set up a test environment, giving them a good Q&A environment.
With two people they were making sales, but there was a lack of technology expertise with only Rob himself working directly on developing the product. At Exemplar, he had worked with Abhijit Chakrabarty who had returned to India to start his own company in Kolkata (Calcutta) to develop...yes, language front-ends. He had great engineers but no real route to market, so they put the two companies "together". I put "together" in quotes since actually Abhijit's company, Electra Design Automation, remains separate but are an exclusive full-time contractor for Verific proper.
At some point after about three or four years, Michiel Ligthart came on as President, to provide overall management, and 15 years ago Rick Carlson came on to take care of sales, which he still does today. Today the company is 18 people. Everyone is in R&D or tech support, except Rick and Michiel and an office manager in India.
The customer base was traditionally EDA companies, especially new ones starting up. Companies like Cadence that have been around from earlier than 1999 usually had been forced to develop their own parsers. Customers receive the C++ source code so they can compile it for any platform they want. They expanded to semiconductor CAD groups, but usually, they didn't have such deep programming expertise and tended to use scripting languages like PERL and Python. Verific developed a shell around the C++ but it never felt entirely natural to PERL and Python users. A couple of years ago, a company called Invionics wrote a shell around the Verific API that worked in Python, by defining a subset of about 50 commands that did 99% of what anyone needed and it worked really well. But they had a hard time selling, so Verific acquired the technology and two of the developers. That is now the Invio product for CAD groups working in Python.
They also have system companies using the front-end, but usually, they don't like to go on the record as endorsing (or even admitting they use) any particular supplier.
Verific currently have 66 active licenses, including the three at Cadence I already mentioned: JasperGold, Rocketick, and Stratus. Over the 20 years of Verific's existence, they have probably licensed more than 100 products, but internal products get canceled, and companies fail. The typical cycle is that a project licenses Verific, they actively work together over the life of the product, and then they stop when the product is end-of-lifed for whatever reason. Their cash-flow is strong enough that they can license poorly funded startups on the basis that they only start paying once they start shipping product.
For any startup project, SystemVerilog is so complicated that developing their own front-end adds nothing, but is a challenge. It's very similar to the value proposition of Cadence's design IP: DDRx interfaces are so complicated and add no differentiation, so why would you build your own (if you even can).
Verific will be at DAC. Unless something unusual has changed, look for the big giraffe. And win a small giraffe by attending a presentation.
In twenty years, Verific has gone from one guy working on his own unpaid (what VCs like to call sweat-equity) to 18 people, and the de facto standard for front-ends.
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