2020 Is the Year of DDR5

I talked recently to Marc Greenberg, one of Cadence's experts on the memory market. Despite the fact that the JEDEC DDR5 standard is still under development, Marc says that:

2020 will be the year of DDR5.

He is excited about it since a new DRAM only comes around every 8-10 years. We had our first DDR5 7nm testchips in silicon almost two years ago, and since then we’ve repeated that in multiple foundries and nodes.

This is another first in terms of DDR IP:

• World's first DDR5 7nm silicon IP
• World's first GDDR6 7nm silicon IP
• World's first LPDDR5 7nm silicon IP

The photograph shows the Cadence DDR5 test board.

In fact, back in May 2018, I wrote about how our preliminary DDR5 IP was operating successfully with Micron's preliminary DDR5 DRAM chips. For details, see my post DDR5 Is on Our Doorstep. That was nearly two years ago. It is still on our doorstep, in the sense that JEDEC has not published the official standard. But it is also on our doorstep in the sense that IP and memories are available, and systems are being designed around them.

I asked him how we could create test chips when the standard is not even out:

Close participation in the JEDEC working groups is an advantage. We get insight into how the standard will develop. We are a controller and PHY vendor and can anticipate any potential changes on the way to final standardization. In the early days of the standardization, we were able to adopt standard elements under development and work together with our partners to get very early working silicon. As we approach the release of the standard, we get more proof points to indicate that our IP will support DDR5 devices compliant to the standard.

Marc also told me 'this is the year for shipping." Cadence already has over a dozen design-ins. He expects to see a ramp of DDR5, driven by actual servers shipping with DDR5 inside. The value proposition, especially early on, is most attractive to enterprise, cloud, big data applications. In these initial shipments, 4800 will be the speed, which is just one speed bin above that early experiment with Micron that I linked to above. Eventually, the speeds will go higher, but 4800 will be the introductory speed. The chart above shows the switch from one DDR technology to the next. Note the red line that shows mobile DRAM, which is growing to be half the entire market for DRAM.

As Marc told me:

DDR4 went to 3200 just this year. Adoption of DDR speed grades happens quite slowly. DDR5 is the next step. It is a big leap in bit rate performance. But it will then hang there for 12-18 months, then go up to 5200, and 5600 after that. We are back on the treadmill of one speed grade every 12-18 months.

In fact, the goals of DDR5 are:

• Larger dies while managing timing challenges
• Solve retention time problem (with on-die ECC)
• Same speed DRAM core with higher speed I/O
• Increase one speed grade every 12-18 months

Marc emphasized the DDR5 is more about density than speed. Using DDR5 it should be possible to have 512GB memory per channel for large dataset computing. When DDR4 was introduced, 16Gb die was impossible—now it is merely challenging. That is the entry capacity for DDR5, but it is expected to go to 24Gb and eventually 32Gb.

DDR5 is also quite well suited to stacking, so we can expect to see stacked devices allowing for even further capacity expansion. One is 3D. The other is LRDIMM technology, which allows for increased capacity. LRDIMM (LR stands for "load reduction") is a tiny sliver of the market but it may be important for some system designers.

With DDR5 we will have 256GB DIMMs, with two slots per channel, so a 512GB machine. But wait, there's more:

A lot of these machines have 8 channels on a processor die, each die with 512GB, making a 4TB memory machine where you can access any byte in under 100ns. If a database index is 4TB, you can imagine how big a database could be supported. Quite a beast.

 

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