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A few weeks ago, there was a webinar about designing 3D-ICs with Innovus Implementation. Although it was not the topic of the webinar, I should point out that if your die is more custom/analog, then you can also design 3D-ICs in the Virtuoso environment. And if your design is more focused on the package, then you can design 3D-ICs in an Allegro environment. Many 3D-ICs will involve all three aspects and may well end up using all three tools. Innovus Implementation is focused on digital design, and in the context of this webinar, designing digital 3D-ICs. The webinar was presented by Indu Dhingra.
Consider this the obligatory paragraph about the slowing of Moore's Law and the rise of advanced packaging under the name More than Moore. In the past, packaging was almost an afterthought. It was there to do a few things, mostly protect the die and fan out its signals to pins on the package for connection to the PCB. In fact, it wasn't always used, and sometimes the die would be attached directly to the PCB, and then covered by a blob of epoxy, known as chip-on-board.
Today, advanced packages are about adding value and creating an alternative universe as a way of delivering systems on silicon, in comparison to integrating everything onto a single large die. There are several drivers for this, such as only part of a design requiring the most advanced nodes, smaller die yielding better than large die, the largest die exceeding the reticle limit, higher performance if all the die are closer, and so on. The image shows one example of the sort of design that we are discussing: an interposer, with several die, an HBM memory stack, an analog die, a die containing all the high-speed SerDes, and a processor. This webinar was about how you actually go about building something like this.
Before we get to Innovus Implementation, one more tool: the OrbitIO Interconnect Designer is used to handle the top-level of a multi-die design. It keeps track of the golden schematic that links all the die together, and it can handle designs that use any combination of the Innovus, Virtuoso, and Allegro environments, and all the corresponding verification and signoff tools.
There are two primary types of 3D-IC, stacked die and interposer based. See the diagram. The term "stacked die" means that there is one die at the bottom with thru-silicon vias (TSVs) to get signals to the upper die. The upper die is flipped over so that its "top" is facing down. There might be one or more additional intermediate die, which also require TSVs. The interposer approach, sometimes called 2.5D, has an interposer (silicon, glass, organic) and all the other die are flipped and then attached to the interposer. The interposer contains routing, known as the redistribution layer or RDL, and has to have a way for signals to pass through it (TSVs if it is a silicon interposer).
There are three key aspects to 3D-IC from a physical design point of view:
Innovus Implementation has been enhanced to handle these three features. TSV is modeled as a via between M1 and MB. MB is modeled as a routing layer. Micro Bump is modeled as a macro, in the same way as for a normal flip-chip design. Of course, there are added commands to control all of this. Some of that was covered in the webinar, but that is going too deep for a blog post like this. Innovus Implementation also handles the constraints between the die. The hard constraint is that the die that connect a net through a micro bump need to be aligned (so that the required connection is made during assembly). A soft constraint is to minimize the wire length for die-to-die interconnection.
The bump file and die abstract are used to communicate between Innovus Implementation runs on different die. The diagram shows two die being run through Innovus Implementation for physical design and then signoff. After the floorplanning is done (and so everything is placed), the two flows have to be synchronized to make sure that when the die is flipped, the pads line up on the micro bumps, or if it is a TSV die, that the TSV land on their own micro bumps on the backside of the die. For an interposer-based 2.5D design, the interposer also needs to be done (in the Virtuoso environment), although again the communication is done using the bump file.
The Pegasus Verification System is used to do all the DRC. Of course, the die all need to be checked in the usual way, but the Pegasus system also checks all the die-to-die connectivity, which is basically the bump alignment, ensuring that when the die are flipped and stacked so that everything lines up and will connect automatically during assembly.
3D-IC designs have potentially greater thermal and EM challenges than a "normal" 2D design, since the die at the bottom of the stack are thermally insulated by the die above. If there is a heatsink, for example, they are further away from it (not just physically, but thermally).
The Voltus, Sigrity, and Celsius solutions are used together to do electrical/thermal analysis. These need to be done together since thermal is affected by power on the die, but power on the die is affected by temperature.
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