Memory Standards and the Future

I sat down and talked with Amjad Qureshi recently He is vice president of research and development for the DDR PHY and controller IP. My first assumption, that he joined Cadence with the Denali acquisition, turned out to be wrong. But he does have a 25+ year long history of industry experience in IP, semiconductor, and electronics companies such as Samsung, IBM, Dell, Adaptive Chips, and Cradle Technologies. Most recently he was at ARC, which was acquired by Virage, but he left and joined Cadence before the acquisition of Virage itself. He has been at Cadence for seven years.

Memory has changed a lot since he has been involved, in both the design of memory controllers but also with the JEDEC standardization process. Denali before and now Cadence are the leaders in IP for memory controllers. For the enterprise market there is a focus today on DDR4 with a maximum data rate of 3200 Mbps. These are normally used in DIMM modules.

Ten years ago the industry started with LPDDR1 and now are up to LPDDR4. These technologies have been focused on mobile- and battery-powered devices, with both lower power and smaller physical size. Consumer customers today want a super combo of LPDDR and DDR (usually a combo of DDR4 and LPDDR4) with the 4.266 Gbps data rate. But IP has to be configurable to meet the PPA requirements, in particular keeping the power and area under control.

I asked Amjad what is coming in the future, both at Cadence and in the memory market in general. The next thing is a new version of LPDDR4 called LPDDR4x which has an operating voltage of 0.6V (compared to 1.1V for LPDDR4). There are proposals for LPDDR5 with much higher data rates but the standards are not yet finalized. There are other developments, in particular with 3D "memory on logic" approaches. One is high-bandwidth-memory (HBM) with TSVs, where a very wide data bus is created between the logic chip and the memory chip on top. There are also other wide I/O controllers and specialized memories where Cadence is working closely with the foundries to ensure manufacturability.

A big challenge in memories is that the JEDEC requirements get tighter and tighter as the data rates increase. For example, currently from PLL to memory and back, the clock can only have 2% variation. This means that it is necessary to model the entire memory subsystem, including both the analog and digital from end to end. The physical configurations, such as package-on-package (POP) or DIMM, also effect this and need to be taken into account.

Another challenge is managing signal integrity. For this, Cadence uses a virtual reference design (VRD) which can model any protocol with choices of memory topology and channel. Until LPDDR4, this was a parallel interface but now it is all at SerDes data rates. The packages can have up to six layers, the board can have many, and extensive use in the VRD is made of the Sigrity SI tools. A full analysis of decap requirements is also essential for working systems.

Cadence offers DDR controller and PHY IP that supports all widely used DDR protocols, including LPDDR4, LPDDR3, LPDDR2, DDR4, DDR3, and DDR3L. The DDR Controller IP is extremely flexible and can be configured to support almost any application. Two DDR PHY architectures, high-speed (HS) PHY and low-power (LP) PHY, are designed to provide configurable solutions. Learn more about Cadence's DDR and SDDR portfolio here.

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