An Steegen's Secrets of Semiconductor Scaling

If you were asked where in the world the most leading-edge semiconductor research is done, you'd probably pick the US or perhaps Taiwan. But the real answer is Belgium. Not even Brussels, but Leuven, a small town about 15 miles to the east where imec is located. imec holds a number of technology forums each year, the largest in Brussels for two days in May, and a shorter half-day one the day before Semicon West in San Francisco in July. One of the highlights is always listening to An Steegen, who is in charge of process technology at imec. It is like drinking from a fire hose but you get an update on what the funnel of new semiconductor technologies looks like and where the consensus seems to be coalescing around the technologies that the industry will adopt.

An said that for years designers have had "happy scaling" where PPA all improves due to Moore's Law and Dennard scaling: More transistors for the same cost and the same power density. But that has all broken down. Dennard scaling assumes that almost all the capacitance is due to the transistors, but that's not been true for a long time. For a decade, we've not had happy scaling, which leads to dark silicon, the capability to put a lot of transistors on a chip but not to fire them all up at once.

So what does the future hold? We need EUV, like yesterday. Then we can do 7nm node with 32nm pitch single patterned. Right now the dose is reasonable, but there are still issues with line-width roughness (LWR). To keep some semblance of Moore's Law going, we need to get the costs down for 7nm. The keys are MINT (intermediate metal), SAGC (self-aligned gate contact), and buried rail, which allows the standard cell height to be reduced from 9 track to 6 track leading to a bit density increase. This is design technology co-optimization, not just optimizing the transistors without worrying about how they might get used.

To go beyond 7nm requires horizontal gate all around (GAA) nanowires, which have even better performance than FinFET. Adding III-V materials improves the performance even more and imec has successfully manufactured prototypes that perform better than pure silicon. Nanowires require at least a double stack, otherwise they don't perform better than FinFET so "why bother." They perform at very low supply voltages but since nothing has been ramped to volume, there remain questions about cost-effectiveness. They also have better electrostatic behavior than FinFET.

So much for the front-end-of-line (FEOL). What about the metal (back-end-of-line)? There is no point in just improving the transistors if the metal goes the wrong way and we need to get the resistance down. In particular, we need to extend the life of copper, perhaps with liners of rubidium (Ru) or cobalt (Co), perhaps even replacing copper in the vias with cobalt.

But without voltage scaling, there is a major battle between design/technology and dark silicon. Techniques like dynamic voltage and frequency scaling can buy some one-time relief, as do FinFET and nanowires. Sooner or later we will need to find the next switch. An says the the most promising approaches are tunnel FETs, which can provide a 3X drive current improvement, and Spine Wave majority gates, which allow for a 100X improvement in energy efficiency (but are slow). Existing memories are also challenged with the need for something to fill the gap between DRAM and solid state disks. imec is working there, too, on MRAM and RRAM approaches.

3D approaches are also promising, with logic on the bottom and multiple layers of memory on top. This gets the memory bandwidth up, which is a big deal for traditional (von Neumann) computing, although the more layers you stack the more stress goes up on the wafers. To go further, to keep compute power improving, might require going away from the von Neumann model to something closer to brains, neuromorphic computing.

We have gone from pure technology optimization, to design technology co-optimization (standard cell heights and so on), and next is system technology co-optimization. Transistors alone can't carry the entire load.

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