Analyzing On-Chip RF Passives

RF stands for radio-frequency. Obviously, this covers radios of all types, but as Brad Brim said to me when I interviewed him on his retirement (see my post Brad Brim and the History of Signal Integrity) "digital signal frequencies are in the range that we used to call microwave". So if you are designing, say, a 112G SerDes then you are dealing with the same type of frequencies as 5G mmWave. In fact, serial interfaces are likely to get more like radios in the future, since the smart money is on next-generation interfaces using quadrature amplitude modulation (QAM) rather than PAM-8, thus making use of phase as well as amplitude. This is used by all mobile phone radio interfaces.

RF design involves passive components. Resistors and capacitors, obviously. But also inductors, transformers, and baluns. A balun is a special type of transformer than converts between a balanced and unbalanced signal (hence the name, it is a contraction). Older processes, with thin metal and low-resistivity substrate were not really suited to creating these structures efficiently on-chip. I remember years ago analog designers complaining that even resistors and capacitors weren't very good in that era, and the idea building an on-chip transformer was such a joke that a couple of us at VLSI designed one since, finally having a (gasp!) third layer of metal, it was possible.

Once CMOS processes were fast enough that you could even think about designing much of an RF circuit on-chip, these passive components remained on the board (or inside the package). But modern processes allow these components to be created on-chip with equivalent insertion loss to external components, and, obviously, with a lower cost due to saving not just the external components but the I/Os required to access them. In addition, modern processes with large numbers of metal layers, allow high-density capacitors to be manufactured in the interconnect stack. These are usually called MoM, for metal-on-metal. The diagram shows the type of passives that can be analyzed, from more basic ones in the top row, to more complex ones in the second row:

Electromagnetic (EM) Simulation

Obviously, fast and accurate modeling of these integrated passives is important. There are three main aspects to this:

• EM simulation for the RF designer to evaluate candidate designs and optimize the physical design
• Converting the results into models that can be used in simulating the rest of the chip
• Using EM simulation to detect parasitic coupling between components, or between components and interconnect.  As frequencies become higher, this unintended coupling can severely degrade a circuit’s performance

EMX is the main product we acquired with Integrand Software, earlier this year. For more background on that, see my posts Designing Radios: Integrand and The Integrand Story. EMX is used for on-chip analysis of passive RF structures. As I said in the opening paragraphs, increasingly passives are moving on-chip. Integral formulation (sometimes called boundary element) approaches like EMX are most appropriate when the enclosing dielectric is largely planar. Well, integrated circuits are certainly largely planar and the passives are all planar. At the next level of detail, semiconductor layers really are (almost) planar, with vias between the planes. EMX uses an algorithm computational software called the Fast Multipole Method, which is both faster and more accurate than doing a fully-general 3D analysis and can often take advantage of the planarity. This algorithm has actually been considered to be one of the top 10 algorithms in computer science in at least one top ten list.

The big advantage of the differential formulation of Maxwell's equations is that only the conductors need to be meshed and modeled. All the dielectric and substrate effects can be dealt with using a Green's Function. You might guess that Green was someone who did his work recently, but in fact, his paper An Essay on the Application of Mathematical Analysis to the Theories of Electricity and Magnetism dates to 1828, almost 200 years ago. James Clerk Maxwell was born after that date, and Maxwell's Equations are partially based on George Green's earlier work.

Integrated circuits are more than mostly planar, they have several other advantages that can be used to optimize calculation:

• IC layouts are very regular and instances are often repeated (such as via arrays, or repeating the same inductor more than once)
• Wires tend to be paths of constant width, and the distance between adjacent wires is often constant, too
• Routing is almost always either horizontal, vertical, or at 45°

As an example of the regularity that EMX exploits, the above diagram shows a wire mesh with the isomorphic shapes colored. EMX takes advantage of this regularity to avoid repeating computations, reducing both the runtime and the memory requirements.

However, not everything is well-behaved on an IC. The biggest issue is variability during manufacture, which deserves a section of this post of its own (below). A few other difficult areas where attention is needed:

• In order to accurately model IC layouts, it is important to simulate skin-effect and sidewall capacitances correctly
• For MoM capacitors in particular, a 2.5D approximation using thin conductors is not sufficient, so EMX uses a volume integral that treats conductors and vias as 3D objects
• EMX uses a special representation of the vector potential interactions, normally the most computationally expensive part of the simulation, and this representation allows the vector potential interactions to be computed with about the same cost as the scalar interactions

Variation

Advanced semiconductor processes are not completely perfect, there is variation from wafer to wafer and even die to die. The physical width, thickness, and resistance of a wire varies statistically, and can also be affected by the surrounding wiring. This is especially true below about 28nm where optical proximity correction (OPC) is required since the feature sizes are smaller than the 193nm light used for the lithography. It is even more true at 16nm and below where multiple patterning is required on some layers (EUV probably improves this but RF experience with chips built using EUV, second-generation 7nm and below, is limited). Some factors, such as sheet resistance, can vary significantly from their nominal value. Clearly, these large variations can affect the EM performance and so it is important to account for them in simulation and modeling.

Foundries provide detailed information about pattern dependencies, usually in the form of tabulated data indexed by wire width and spacing. Internal to EMX, the input drawn layout is automatically modified using these tables to accurately model the structures that will actually be fabricated.

For simple layout, such as multiple parallel wires, terms like width and spacing have obvious meaning. But EMX needs to handle more complex layout involving non-uniform structures, but using only tables indexed by width and spacing. To handle this, EMX uses Voroni diagrams to analyze and partition the layout into non-overlapping regions. Then maximally sized circles can be inserted, and these can be taken as local approximations of the spacing. The local width is calculated in a similar way with circles inside the conductor. The diagram below shows an example (showing only the spacing circles):

Typically, the most significant fabrication effect is that the manufactured line width varies from the drawn width by a bias amount that depends on the local width and spacing in the layout. The bias amounts come from the table already described above. The table, being tabular, only has certain values and interpolation is used to compute bias as a continuous function of (drawn) width and spacing.

An Example

As an example, let's use the voltage-controlled oscillator (VCO) that appeared right at the start of this post as an example of the sort of structure that VCX can analyze.

The diagram above shows the VCO, fabricated in a 6-layer 90nm CMOS technology. It consists of an inductor and a bank of 66 MiM capacitors that are switchable for tuning. The inductor here is small, enough so that parasitic coupling between the inductor and the interconnect and the details of how the capacitors are hooked up must be considered. Indeed, a block-by-block model failed to predict the VCO’s behavior. Using EMX to simulate the whole structure at once gave accurate results. The simulated and measured tuning curves are shown below. The red line shows values measured from silicon; the blue line shows values calculated by EMX.

Integration

EMX is integrated into the Virtuoso design environment. You can work on layout of your design or a particular passive, and then run EMX to perform analysis without leaving Virtuoso. You can also automatically create Spectre models of the results of EMX analysis and then simulate them in Spectre (along with other Cadence Spectre models).

An RF Joke

I know these two RF engineers who got married. The wedding was only okay, but the reception was fantastic.

Learn More

See the EMX Planar 3D Simulator page on the Cadence website, or download the EMX datasheet.

The four bullet summary is:

• The fastest EM simulator for IC design based on the Fast Multipole Method (FMM), more than 10X faster than other commercial EM tools
• EMX Planar 3D EM simulator with highest-in-class accuracy because of volume mesh formulation for conductors
• Supported by all foundries and extensively validated against silicon measurements
• Seamlessly integrated in Virtuoso environment for ease of use

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