Automatic Testbench Assembly

Every so often there is a change in the level where design gets done and, thus, a change in the tools and methodologies that are required. The last big change was the switch from gate-level design to RTL design requiring high-performance RTL simulation, automatic synthesis, static timing analysis, and more. The general expectation a decade ago was that the next change would be a move to higher level specification, perhaps in C or SystemC. There has been some movement in this direction with high-level synthesis (HLS) being used more and more for designing new IP blocks on a variety of different design types, no longer limited to purely algorithmic data processing blocks.

The dominant change has been the switch towards IP-based design. Many systems on chip (SoCs) today consist of 80-90% IP blocks and 10-20% of new RTL created for the chip. In some cases the IP content approaches 100%, the chip is basically just an assembly of IP blocks with the differentiation provided by the way the blocks are put together and by embedded software.

The IP blocks can come from a number of sources: 3rd party IP provided by specialist companies such as ARM or Cadence, IP created in IP groups within the same company, and IP being re-used from prior designs. However, the tools and methodologies to support this style of design have been slow in coming. Most SoC development flows were built many years back and are optimized for handling newly created RTL.

Following on the heels of reusable IP was reusable Verification IP, or VIP. The first step towards this more structured verification approach was the creation of the universal verification methodology (UVM) standardized by Accellera and supported by all the major EDA companies.This was based on a prior open verification methodology (OVM) developed jointly by Cadence and Mentor. UVM version 1 was finalized by Accellera in 2011. UVM is targeted at IP blocks and subsystems, making verification more systematic.

However, UVM doesn't address the SoC integration challenge where SoC design teams spend most of their time. A large part of that time is spent on verification to make sure that the integration is working and to help solve integration issues. UVM is one building block for what is needed.

Another building block is IP-XACT. This is an XML machine-readable format, created by the SPIRIT consortium, to enable automated configuration and integration. An IP block along with its IP-XACT meta-data can be read by automated tools and then can assemble the whole system. IP-XACT was approved as an IEEE standard, originally in 2009 and then most recently there was a new version of the standard, IEEE 1685-2014.

Obviously, one aspect of SoC integration is the RTL design since all the IP blocks need to be assembled for a specific chip development. A newer area of automation is testbench assembly based on VIP building blocks. There are finally starting to be some projects in this space and 2016 is likely to see a lot of advances in providing a suite of tools that can automate taking the UVM and the IP-XACT and creating different testbenches to verify that the blocks, buses, and networks on chip are all correctly assembled.

As the largest IP vendor, ARM recognized this as a major challenge and obviously have a lot to gain by improving the IP integration process. They have a number of products such as AMBA® Designer that can be used to describe the design and which then creates the IP-XACT, and a couple of years ago they acquired Duolog, a startup that had a tool called Socrates that allows designers to specify the design.

Cadence has automation tools like the Interconnect Workbench which can read the output of tools like AMBA Designer or Socrates and create a testbench to functionally verify the interconnect and memory subsystem of an SoC and enable performance analysis. The inputs are VIP for the various blocks and the metadata. This considerably reduces the turnaround time for the integration effort. Another type of testbench that can be created verifies all the bus registers, of which a large SoC may have thousands, and check either through simulation or through formal techniques that they are all appropriately accessible.

One of the challenges as the level of SoC assembly automation improves is to ensure that the meta data is accurate. This has always been a problem with the old way of doing things using paper documents. If the designer adds a new register, the documentation needs to be updated so that the software team can access it. Things are considerably improved using IP-XACT, but more work needs to be done to decrease the amount that still needs to be done manually.

Today, much of the work in this area is still preliminary, joint projects involving customers, IP companies, and EDA companies. But expect to see real products start to appear. 2016 will be the year of automatic testbench assembly.