Tom Beckley's CDNLive Keynote: Addressing Complexity and Safety Challenges

Tom Beckley gave the final keynote before lunch here at CDNLive in Silicon Valley. To set the scene, he told the story of watching the Space Shuttle Challenger launch in Florida where he worked for Hughes at the time. It was January 28, 1986, and as we all know it was a flight that lasted just one minute sixteen and a half seconds before the shuttle started breaking up with the loss of the entire crew. It wasn't due to the failure of a chip, of course, but the space shuttle was the most complex vehicle designed at the time, a system of systems. Smartphones are systems of systems, too.

As are modern cars, which often contain more than 100M lines of code. Beckley pointed out that 2014 was the worst year for recalls ever. Except for 2015. So far for 2016, it is looking worse. It is not just cars. The FDA reported that last year there were over 2,000 medical device recalls. System-level defects are the most difficult to cope with. They make up only 8% of the total defects but take over half the effort to repair, whereas unit-level defects make up the remaining 92% but in aggregate are just under half the effort to repair.

In the semiconductor ecosystem, everyone is very aware that the cost of design is going up at each more advanced node, and software is a large part of the overall system cost. In fact, a good rule of thumb is that the cost of the software for a project is about the same as the entire cost of the previous project, a sort of negative version of Moore's Law.

The result of all of this is that functional verification and safety is the new reality in which we now live. In automotive, it is ISO 26262, in IEC 60601 and 62304. Security in IoT devices is a story unfolding every day.

System Design Enablement is the capability to pull all this together: the chip, of course, which is the heart of what Cadence has done for decades. But complex packaging, increasingly 3D. Boards with aggressively fast signal protocols. Complex system integration including the stack of software from device drivers to operating system, networking, and application levels. Cadence has a broad portfolio of verification, from simulation (including fault injection for functional verification), emulation, formal approaches, and more. One major bottleneck on almost every chip is analog. It only makes up a small part of the chip area compared to the digital but it dominates the design and verification effort since almost everything has to be done manually with limited automation.

Virtuoso is 25 years old this year and, at CDNLive, the new Virtuoso ADE Verifier was announced. ADE Verifier allows analog tests to be tracked along with the digital, extending metric-driven verification across the whole of any mixed-signal SoC without requiring the analog blocks to be replaced with specially created models that function in the digital world but are not adequate for analog verification, which needs to be done at the transistor level.

In fact, there are four new products in the Virtuoso product family:

• Virtuoso ADE Explorer
• Virtuoso ADE Assembler
• Virtuoso Variation Option
• Virtuoso ADE Verifier

These products allow the verification team to map requirements to tests, run tests and verification, track results, and do functional safety reporting.

The new capabilities extend the arsenal of verification capabilities to analog, to go along with verification of boards, packages, chips, digital logic, and running real software loads, tying everything back to requirements and complying with the increasingly important functional safety standards for different markets.

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