DesignCon is Back In-Person and Cadence Will Be there

DesignCon is coming up April 5th to 7th. It takes place in the Santa Clara Convention Center. We will be there with a real booth, number 927. DesignCon is a somewhat confusing name for the conference. In the past, I've said it should be called the signal integrity conference, since many of the exhibitors are focused on signal integrity tools and IP (Cadence), or on measuring signal integrity (all the oscilloscope guys), or improving it at the connector level. It is somewhat odd to find presentations on our Clarity product a couple of booths over from a company from China selling low-loss coaxial connectors and ribbon cables.

Our self-described motivation for visiting the Cadence booth is:

to see how you can improve your electromagnetic, electronic, and thermal designs with system analysis, tackle advanced IC packaging and cross-platform challenges, and successfully incorporate photonic ICs and designs with 112G SerDes and PCIe IP

We have six main demos (although I'm sure we can find someone to talk to you about almost anything):

• Interposer/package/PCB signal and power integrity analysis
• Scalable 3D electromagnetic (EM) modeling solutions for interposer/package/PCB
• System-level electrothermal co-simulation featuring solvers for fluids (CFD) and solids (FEA)
• End-to-end design flows for silicon interposer (2.5D-IC) and vertically integrated chip stacks (3D-IC)
• 112G extended long-reach SerDes for next-generation data center, AI/ML, and 5G applications
• How to solve complex photonic IC challenges using an integrated electronic/photonic design automation (EPDA) environment

However, there is more going on than just a booth in the exhibit hall. We have people on panels and some presentations during the conference itself. Then, Thursday is educational day when we will be taking over Mission City Ballroom B5 for the day and delivering a series of free educational presentations. Details below.

Sessions in the Conference (Tuesday and Wednesday)

Panel—AMI Models and the Seven-Year Itch
Tuesday April 5th 4:45–6:00pm in ballroom AB
Panelists:

• Ken Willis, Cadence
• Walter Katz, MathWorks
• Randy Wolff, Micron
• Aleksey Tyshchenko, SeriaLink Systems
• Michael Mirmak, Intel
• Donald Telian, SiGuys

 A Step-by-Step Guide to a Novel Lab Correlated PDN Co-Simulation Methodology
Wednesday April 6th 8:00–8:45am in ballroom F 
Speakers:

• Idan Ben Ezra, Broadcom Semiconductors
• John Phillips, Cadence
• Ilan Wolff, Arista Networks

Optimal Design of High-Speed Flexible Interconnectors by Applying Bayesian Optimization and 3D Electromagnetic Solvers
Wednesday April 6th 9:00–9:45am in ballroom F
Speakers:

• Kyle Chen, Microsoft
• Suomin Cui, Cadence
• Grace Yu, Microsoft
• Jian Lui, Cadence

Long-Haul Inter-Domain Power Noise
Wednesday April 6th 11:15am–12:00pm in ballroom H
Speakers:

• Ethan Koether, Project Kuiper – Amazon
• Shirin Farrahi, Cadence
• John Phillips, Cadence
• Kristoffer Skytte, Cadence
• Joseph Hartman, Oracle Corporation
• Sammy Hindi, Ampere Computing
• Istvan Novak, Samtec
• Mario Rotigni, STMicroelectronics

PCI Express Technology: Evolving   Automotive Connectivity for the Next Generation of Vehicles
Wednesday April 6th 2:00–2:45pm |in ballroom C  
Speaker: William Chen, Cadence

Keynotes

There are three keynotes during the conference that all seem like they will be interesting. They are:

• Tuesday 12-12.45pm John Bowers, Fred Kavli Chair of Nanotechnology, University of California, Santa Barbara Progress Enabled: The Convergence of Photonic & Electronic ICs
• Wednesday 10.15-11.00am Laurence Moroney, Artificial Intelligence Lead, Google The Realities of AI & Machine Learning: Cut Through the Hype & Move to Production
• Thursday 10.15-11am José Morey, Consultant for NASA, IBM, Hyperloop Transportation, and Liberty BioSecurity Space Tech: Present & Future

Educational Sessions (Thursday)

All presenters are from Cadence unless otherwise noted.

• 9.00-9.45am Sherry Hess No Exit Ramps Needed—Cadence's System Design Workflow Delivers Seamless In-Design Analysis, Reducing Turnaround Time and Minimizing Risk
• 11.00-11.45am Ken Willis Overview and Challenges of Running D2D Interposers
• 12.00-12.45pm Michale Rowlands (Amphenol) and David Correia Addressing 112G Connector+PCB Modeling without Having to Simulate with Terabyte Servers
• 1.00-1.45pm Xin Chang (Meta) and Ken Willis MIPI C-PHY System Design Exploration and Optimization for Signal Integrity Analysis by Using Advanced Cadence Compliance Kit
• 2.00-2.45pm Tony Chen and Jared James Mainstream Signal Integrity Workflow for PCIe 6.0 PAM4 Signalling
• 3.00-3.45pm Wendy Wu The Future of 224G Serial Links
• 4.00-4.45pm Kyle Chen and Suomin Cui Optimizing Interconnect through Application of Bayesian Optimization Using 3D EM Solvers
• 5.00-5.45pm Karthick Gopalakrishnan Electrothermal Co-Simulation for PCB and Package Designs Using Celsius Thermal Solver

Learn More

See the Cadence DesignCon page.

See the DesignCon 2022 website.

Sign up for Sunday Brunch, the weekly Breakfast Bytes email.

.