Breakfast Bytes Blogs

One of the potentially significant events in the foundry marketplace is the creation of Intel Foundry Services (IFS). This was announced by CEO Pat Gelsinger after about a month in the new job, and I wrote about it in my post, The New Intel Foundry Services. As I pointed out there:

Just a bit of background. Intel has attempted to build chips for other companies before. They started up an ASIC business in the 1980s. I was at VLSI Technology competing with them, but the received wisdom at VLSI was that Intel would not last long once it discovered that it could not make the same revenue per ASIC wafer as it could with microprocessors. And indeed, Intel shut it down fairly quickly. Then, a few years ago, Intel started up a foundry business called Intel Custom Foundry or ICF. I don't recall them ever announcing any marquee customers apart from Altera (who it acquired). I don't think ICF was ever officially discontinued, it just faded away.

I have to say that this time Intel seems to be serious about making the foundry business a success and not using it as some sort of adjunct business unit to go along with the "real" business of building x86 processors. When Pat originally announced IFS, there was obviously a lack of details: what processes? What timeframes? Which fabs? What about IP?

Well, at the recent CadenceLIVE Silicon Valley (which took place approximately five minutes from Intel HQ) Lluis Paris filled in quite a few of those details in a presentation titled Cadence and Intel Foundry Services: Let's Build the Future Together.

Lluis started with some of the motivations for Intel to re-enter the foundry business:

• Semiconductors are critical to the global economy
• Shortages and geopolitics are key concerns for leaders
• Strong momentum since IFS launched
• Innovative foundry with global scale

You have probably already heard some of the background to that last bullet. Intel announced two fabs in Arizona when IFS was first announced. They have since announced a fab in Ohio and one in Magdeburg, Germany. For completeness, they also have fabs in Oregon, Ireland, Israel, and New Mexico. They are also acquiring Tower Semiconductor, which has seven fabs all over the world. This allows them to claim truthfully that they are the only company that can provide balanced manufacturing at scale is Intel.

As always, the devil is in the details. There is a lot more to a modern foundry than just manufacturing. The above chart double-clicks one level down into the offering:

• 0.5um to leading-edge silicon and advanced 3D packaging. I think the 0.5um is Tower, so this assumes the acquisition goes through. Intel's advanced packaging goes under the names Foveros and EMIB (for embedded multi-die interconnect bridge)
• Support of the three main instruction set architectures (ISAs): x86, Arm, and RISC-V. Indeed for RISC-V, Intel has set up a fund to finance startups in the space.
• Robust IP ecosystem from both Intel and 3rd parties (like us, see below for more details)
• Industry leading innovations such as chiplet open platform. I'm not sure if this is just a reference UCIe, which was originally created by Intel before being donated

Business Models

IFS has a flexible business model, in the sense that the customer can do some part of the process and Intel the rest. For example, you can get other foundries to build the silicon and then use Intel for advanced packaging, as has been announced with Amazon AWS being the first foundry customer for EMIB.

The diagram above shows how this can work, with Intel just being an assembly house (OSAT, which is outsourced assembly and test). The next line down is the traditional foundry model where the customer delivers layout to Intel, and Intel does some backend processing but basically is just manufacturing, assembling, and testing the product. The ASIC model is where the customer creates the design, but Intel does the physical design and timing closure. The last two lines are businesses Intel already does, whereas for the biggest hyperscalers Intel produces derivatives of their server products (CSSP stands for customer-specific standard product).

IFS has strong first-year momentum, Lluis said. Here's a quote from one of Intel's first customers, Cisco's CEO Chuck Robbins:

In less than a year, IFS has created a world-class foundry business built on Intel's leadership technologies. Cisco is pleased to be one of Intel's early foundry customers.

They also have the US government commercial foundry contract with RAMP-C partners (including Cadence). They have five anchor prospects in design engagements. There are over 30 customer and ecosystem test chips committed for this year, 2022.

Manufacturing Roadmap

The leading-edge (so not Tower) part of the roadmap is to support customers on Intel 16 in 2022. This is a mature FinFET technology (Intel started in FinFET at 22nm, although they called it TriGate back then). In 2023 they will support customers on Intel 3, which is the last generation of FinFET at 3nm. Then, in 2024, Intel 18A (the A stands for Ångström which is one-tenth of a nanometer, 10^-10 metres) which is a gate-all-around technology (Intel calls that RibbonFET) and PowerVia technologies. These dates are for risk production.

Packaging Roadmap

As I mentioned above, Intel has two advanced packaging methodologies. Foveros allows die to be stacked on top of each other or on interposers. EMIB allows die to be placed alongside each other and then connected. They also have FCxGA used for building large FPGAs (remember, Intel acquired Altera many years ago).

RISC-V

When you think of RISC-V, Intel is not the first manufacturer that comes to mind. But IFS has a big RISC-V initiative to grow the RISC-V ecosystem. They are working with SiFive on a chip/boards known as Horse Creek. They are also partnering (and I believe manufacturing) for several other RISC-V companies beyond SiFive, such as Ventana Micro, Esperanto, and Andes. For more on Esperanto see my post HOT CHIPS: Esperanto's Dave Ditzel and 1000 Minions. Also, as part of this activity, Intel joined RISC-V International.

Design Ecosystem

Of course, Intel is also working on nurturing an ecosystem of EDA, IP, and design services. Part of that involves the qualification of Cadence tools on the planned IFS nodes in the roadmap above. Intel processes are unique and so require native product enhancements.

Intel is also working with Cadence on IP, especially LPDDR5/4X, high-speed SerDes, MIPI, USB, and more. The current portfolio is all on Intel 16 since risk production on Intel 3 is not until next year. See the table above for details.

And with that Lluis wrapped up and took a few questions.

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