Why Attend CadenceLIVE Americas 2021 on June 8 and 9?

Once again this year, CadenceLIVE Americas is coming up soon and it will be completely virtual. As I do each year, let me give you some good reasons to attend. We'd love to give you food and drink but you know why that is not going to happen. We still have giveaways though, even if we have to mail them to you.

First, the dates. CadenceLIVE Americas takes place on Tuesday, June 8 and Wednesday, June 9. The keynotes each day take place from 9-10am PDT, and then conference sessions from 10:15am to 1:30pm PDT. Then you get to do your day job!

1 Lip-Bu Tan's Keynote

Lip-Bu Tan, Cadence's CEO, will open the conference with a keynote titled Harnessing the Power of Analytics—Driving the Electronics Industry Renaissance.

The electronics industry renaissance continues to drive change and growth in semiconductor design. With the increasing influence of hyperscalers comes a restructuring of the ecosystem as they drive priorities for process nodes, packaging, PCBs, and complete systems. Productivity designing software for intelligent systems is an increasingly important bottleneck. Data analytics are at vanguard of this wave of change, and Cadence is a key enabler of the technologies fueling the innovation.

By the way, you have to watch Lip-Bu's keynote live, like all the keynotes. It will not be available for replay afterward.

2 Anirudh Devgan's Keynote

Anirudh Devgan, Cadence's president, will give the opening keynote on the second day with a presentation titled Electronics Systems Design—Cadence Technology and Innovation Update.

Successful design of high-performance electronic systems demands a level of system engineering previously seen only for rocket science and theoretical physics. Engineers are striving for optimal capabilities while squeezing margins for cost, size, power, and other factors. Incorporating intelligence requires another level of control theory beyond. To achieve desired results requires a new approach of Intelligent System Design encompassing semiconductor, electrical, mechanical, and thermal effects. Hear about the latest innovations from Cadence that achieve results and enable higher quality design with the industry’s best designer productivity.

3 Tuesday Invited Keynote: Google

Tuesday's invited keynote is by Google's Partha Ranganathan. Partha is a VP, technical Fellow at Google where he is the area technical lead for hardware and data centers, designing systems at scale. Prior to this, he was a HP Fellow and Chief Technologist at Hewlett Packard Labs where he led their research on systems and data centers. He has been named a top-15 enterprise technology rock star by Business Insider, one of the top 35 young innovators in the world by MIT Tech Review, and is a recipient of the ACM SIGARCH Maurice Wilkes award, Rice University's Outstanding Young Engineering Alumni Award, and the IIT Madras distinguished alumni award.

Dr Ranganathan's keynote is titled May I Have More Moore, Please? Thinking Outside the Traditional Hardware Box.

Growing volumes of data, smarter edge devices, and new, diverse workloads are causing demand for computing to grow at phenomenal rates. At the same time, Moore's law is slowing down, stressing traditional assumptions around cheaper and faster systems every year. How do you respond to the current opportunities, exponentially increasing compute capacity at a fixed cost? Specifically, we will discuss the innovations and trends shaping the future computing landscape—more “out-of-the-box” designs that consider the entire data center as a computer for custom silicon and software-defined infrastructure, and broader open innovation ecosystems.  

4 Wednesday Invited Keynote: Air Force Research Laboratory

Wednesday's invited keynote is by Yadanuth Zambre, Chief Microelectronics Technology Officer (CMTO) of the Air Force Research Laboratory (AFRL). 

Dr. Zambre previously led the new ventures initiative for Lockheed Martin where he established two communications start-ups and drove the execution of over $150 million associated programs. Dr. Zambre recently served on the Air Force scientific advisory board. He holds a doctorate from Stanford University in applied physics and a master’s degree and a bachelor’s degree in engineering and applied science from Yale University.

I don't yet have details of Dr Zambre's presentation. I'll drop them in here when I do.

5 Conference Tracks

As usual, there are conference tracks. Note that only some of these presentations will be available for later replay (it depends on the speaker and the speaker's organization). So best is to follow the first rule of politics: "be there". This is the current lineup, obviously subject to last-minute changes.

• 5G/RF on Wednesday (with presentations from NxBeam, Tower, and Cadence)
• Academic Track on Wednesday (UC Berkeley, University of Notre Dame, and University of Colorado, Boulder)
• Automotive on both days (GLOBALFOUNDRIES (GF), Arm, Texas Instruments, and Cadence)
• Cloud on Tuesday (AWS, UC Berkeley, and Google)
• Computational Fluid Dynamics on Tuesday (NUMECA and Pointwise, both of which Cadence recently acquired)
• Custom/Advanced Node on Tuesday (with Intel, ST Microelectronics, and Samsung)
• Custom/Mixed-Signal on Wednesday (with Xilinx, Texas Instruments, and Cadence)
• Digital Design and Signoff on both days (with Arm, Samsung, TSMC, Microchip, Intel, EnICS Labs at Bar-Ilian University, Cisco, Broadcom, Analog Devices, GF, NSITEXE, Renesas, and Cadence)
• IP on Wednesday (Samsung, Beyond Semiconductor, Fraunhofer IIS/EAS, and Cadence)
• Silicon Photonics on Tuesday (Intel, GF, ANSYS/Lumerical and Tower Semiconductor, and Broadcom)
• System Design and Analysis on both days (Broadpak, Fraunhofer IIS/EAS, Deca Technologies, EMA Design Automation, Analog Devices, EMA—Shield Digital Design, EMA—Ologic, Cisco, and Cadence)
• Verification on both days (Renesas, Texas Instruments, Xilinx, Arm, Broadcom, Imperas, and Cadence)
• Verification of IP and Embedded Systems on Tuesday (Imperas, Silicon Labs, and Cadence)

For the detailed schedule including times, see the Agenda by Topic page.

6 Designer Expo

Come and see:

• Arm
• GLOBALFOUNDRIES
• Samsung
• TSMC
• Cliosoft
• UMC
• Doulos
• Google Cloud
• Green Hills Software
• HDL Design House
• imec
• Microsoft Azure
• Sarcina Technology
• Sigasi
• Tower Semiconductor
• ChipEstimate
• Concept Engineering
• EMA Design Automation
• IC Manage
• M31 Technology
• Magwell
• Perforce

and, of course, Cadence.

7 Prizes!

There are prizes. You can get points for all sorts of things, such as filling out your survey at the end of a session you attended, or visiting partners in the Designer Expo, or downloading content. At the end of the show, depending on how many points you have, you can pick various prizes and we will ship them to your home address. One caveat, there is no international shipping. But other CadenceLIVE events are available, maybe in your area!

Giveaways include a travel umbrella, 5000mAh Pebble portable charger carabiner, 16oz Corkcicle tumbler, and a laptop light.

Usual caveat of "while supplies last."

8 A Year of Breakfasts 2021

If you get enough points to get any of the giveaways, you can also get a free copy of the latest A Year of Breakfasts 2021: Systems, 3D Packaging, Cloud, RF, Memory, Deep Learning…and Eggs. Last year my office was full of boxes of books since I ordered enough to give away at DVCon, CadenceLIVE Americas, and DAC. I would have been at all those events and signed your copy. Well, we all know what happened instead. This year, they don't pass through my hands so I won't be able to sign them for you.

The chapters for this year's book are:

• Markets
• Mobile and 5G
• Hyperscale Datacenters
• System Analysis
• PCB and Packaging
• Verification
• Implementation
• IP
• Radios
• Other
• Predictions

The book is also available on Amazon worldwide...around $10 in your local currency.

9 Registration

For more details including registration, see the event page for CadenceLIVE Americas. Or click on the image

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