CDNLive: Design Technology Co-Optimization for N7 and N5

One of the challenges of developing a new node is that there are a lot of moving parts that interact: the process, the design rules, the cell libraries, and the tools. At CDNLive in Munich, Luca Matti presented the work he is doing for N7 and N5. He is doing a PhD at University of Braunschweigen, sponsored by Cadence, but he is actually mostly working at imec in Belgium. He is working on analyzing the implications for design tools and libraries of various potential decisions, a process known as design technology co-optimization (DTCO).

The basic approach is to run multiple experiments with a real design and learn what impact this has on the quality of the design and how it affects PPAC (performance, power, area and cost). The results are shared with the imec ecosystem (which is basically everyone doing advanced process development) and after a six-month window they can also be published and, in effect, disclosed to the public.

The flow used is what you would expect and leads to several areas where there are iterations to co-optimize the process and the tool flow.

• Feedback loop with standard cell design: if there is a very high number of DRC errors then the architecture of the library needs to be changed. If just a few, then those cells should be redesigned.
• Feedback loop with device engineering: providing PPA information for various device options to allow good choices to be made
• Feedback loop with materials/BEOL choices: using PPA information to see the chip-level impact of choices of conductors and dielectrics
• Feedback loop with litho, design rules: comparing the effect of different patterning options
• The EDA loop: since a beta version of the tools will be in use, the tool needs to be enhanced and debugged

One example of these loops in action that Luca discussed was the standard-cell loop. The first attempt at building a standard cell library led to a very low (60%) placement density. The tool was enhanced to better handle metal1 in the cells and mpt vias. The result was 75% density and DRC error free. So there was a 15% density gain by co-optimizing standard cells and EDA.

Another example is optimizing the metal stack. Two choices were between a stack with 2x32nm, 2x48nm, 2x64nm, 2x80nm versus the same metal1 to metal4, and then 4x80nm. The importance of 80nm is that it can be single patterned and so the manufacturing cost will be lower. The question is how much worse the density and timing will be. It turns out that the final PPA is almost identical, and using the imec cost model, the wafer cost will be 5% cheaper.

The table above shows the timing of the upcoming nodes. The imec N7 work will be finished approximately two years before foundry risk production. Imec then moves on to the next node while the previous generation is brought up in the foundries and process yield is optimized, ready for a ramp to volume production.

This work has shown several examples of how post P&R assessment can successfully provide feedback to standard cell design, to BEOL, patterning and litho choices, and also drive the tool enhancements that are required to support N7 and N5.

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