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Today it is GTC, the GlobalFoundries Technology Conference. I will be there and I will cover what was said later in the week. When I was at CDNLive India a couple of weeks ago, one highly relevant presentation was by Invecas, titled PPA Strategies Using FD-SOI Technology. You might not have heard of Invecas. They are an IP company with a portfolio of what is often called foundation IP: standard cells, memories, IO, interfaces, and so on.
GlobalFoundries licensed FD-SOI technology from ST Microelectronics. If you want to read the story of how FD-SOI came into existence, read my post Silicon on Nothing: the Origins of FD-SOI. GF licensed the technology at 28nm but their customers told them that it wasn't differentiated enough from planar 28nm and so they developed 22FDX, a 22nm version of the basic FD-SOI technology. But this left them with a problem as a foundry, namely the lack of IP. They didn't want to build up an in-house IP group, but on the other hand, as a new player in the market, they couldn't just rely on the "if we build it they will come" approach, and just provide the process and wait for the IP suppliers to simply create a full portfolio opportunistically. It is easy to underestimate this chicken-and-egg problem. I well remember in the mid-1990s that VLSI Technology and other Arm licensees had to fund an RTOS club since companies like Green Hills and Wind River didn't see porting their RTOSes to Arm as a viable business opportunity unless their costs were already covered by Arm and its licensees. Of course, today, Arm could probably charge RTOS vendors for the privilege.
GF could have paid any of the big foundation IP vendors such as Arm to develop their libraries, but a GF executive told me at the time that they were worried that they wouldn't get the focus they needed. Instead, they commissioned Invecas to create their libraries. They were just getting started and didn't create libraries for anyone else and so GF would get the focused attention they needed. Invecas have been working with GF ever since.
At CDNLive India, Surya Narayana Varma Uppalapati presented their work. He started with an overview of FD-SOI. I won't repeat that here. If you want a basic background then I covered it in my post Cadence Tool Suite Qualified for 22FDX Reference Flow. From a design point of view, the big difference between FD-SOI and other processes (planar or FinFET) is that there is a backside gate under the channel. This cannot be used to turn the gate on and off, but it can be used to increase the performance of the gate (forward body bias) at the cost of leakage, or to reduce leakage (reverse body bias) at the cost of performance. This gate voltage can be set statically, it can be adjusted when the chip is first powered up to adapt to the actual corner at which the silicon was manufactured, or it can be varied dynamically (but not fast) in the FD-SOI equivalent of dynamic voltage and frequency scaling (DVFS).
In the years since, Invecas has developed a wide portfolio of 22FDX standard cell libraries, with varying numbers of tracks and supply voltages The above table summarizes the markets, and the most appropriate foundation IP to be considering.
One thing that Invecas emphasized is that in FDX you don't just think PVT as a process corner, you think PVTB, where the B stands for bias. Characterization is done at all the corners shown in the above table. Note that whatever bias you intend to use in your design, the zero bias values are important since the design needs to be functional at power-on and reset, before there is time for any bias to be applied. Otherwise, there is a risk that the circuit would work fine once bias is established, but it can never get there.
There are a number of different practical aspects to using body bias (BB). First is that there need to be special TAP cells to allow the bias voltage to get down to the back gates (wells). These cells are taken care of by the Cadence Innovus Implementation System. The voltages involved in bias can be higher than normal signals, and so special high voltage spacing rules are required, which Innovus honors. As with clocks and power supplies, the bias network needs to be planned as part of the overall design and floorplan, and which parts of the metal stack can be used depends on resistance and capacitance requirements.
The bias voltages are controlled by special cells called body-bias-generators, BBGENP (for p-wells) and BBGENN (for n-wells). These are controlled in turn by a body-bias controller, which monitors the difference between unbiased performance and biased performance, and depending on control registers, drives the BBG cells to actually generate the voltages. The number of BBGENs required depends on the active area (actual standard cell areas times utilization) and biased memory areas. Due to interconnect resistance, the BBGENs are best distributed through the chip.
In addition, it is good practice to have power switches for the biasing to allow support for external (off-chip) biasing both as a backup option and in post-silicon design analysis. The same pads can also be used to monitor biasing when it is controlled on-chip.
Invecas has a broad portfolio of foundation and other IP available.
I would be amiss not to point out that Cadence also has a range of more specialized IP available in FD-SOI processes (28nm, 22nm, and 12nm) although Cadence does not supply standard cell libraries.
As to the EDA tool side, the single sentence summary is that Innovus (and other tools) fully support everything that is required to do FD-SOI designs including well taps, high voltage rules, and more.
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