I haven't been to Taiwan since the last time I worked for Cadence in the early 2000s. At that time, I was running Custom IC, which also included physical verification—we were structured a bit differently back then. However, one reason behind that was that processes were transferred from foundries to EDA companies as SPICE rules and design rules, so having circuit simulation and DRC in the same organization made more sense back then. But in fact, we were in meetings in Taiwan with the foundries to convince them that encapsulating all that and more in a more controlled manner would be a good idea. These became PDKs, or process design kits, although I forget if we'd come up with that name at that point. This would have been at the process node we called "point one three" meaning 0.13 microns, or what we would eventually call 130nm, although I don't think we switched to nm until we got below 0.1um at the following node, 90nm.

Books

CDNLive in Taiwan is mostly in Chinese, although the slides are often in English, so there is only some that I can report on directly. I was largely there to give away copies of my book A Year of Breakfasts 2018 as a way of signing more of you up to receive the weekly Sunday Brunch email. (If you are not already signed up, then you can rectify that error at the end of every single Breakfast Bytes post where there is a "sign me up" button!) One thing that is a bit different here is how many people seem to want to take a selfie or a photograph of themselves with me. I guess it's my five minutes of fame this year, even if I did have to go halfway around the world to get it. See a crowd of happy book owners above.

If you are coming to CDNLive China in Shanghai tomorrow, then I will be there. Come by and get your copy of the book.

Since I was last here, TSMC has opened a museum, the TSMC Museum of Innovation. I will write about that in a separate post sometime in the next few days. I spent some of the spare day that I had there.

The opening keynote was by Chin-Chi Teng, the SVP of the Digital and Signoff Group (DSG) at Cadence. I will cover some of the material he covered in the near future when I will have some posts about Intelligent System Design.

Yu-Chin Hsu

Yu-Chin Hsu, the Deputy Minister of the Ministry of Science and Technology, gave a keynote titled Driving Tech Innovation in Taiwan.

Ten years ago, I wrote a joke post on my old blog EDAgraffiti about The All-Purpose EDA keynote (Aart de Geus assured me he'd been following my rules for years) but it is very out of date. The modern keynote has to talk about how we are either in the fourth industrial revolution (for example see my post CDNLive Japan: The Fourth Industrial Revolution and the Third Dimension) or better still stretch it out to five so that you can play with "5G", as Yu-Chin did:

But even more important, every keynote has to talk about AI, just as every startup has to be an AI startup (or at least say it is). Joking aside, Taiwan's Ministry of Science and Technology has four big AI grand strategies, that they think of as "grand challenges".

I'll just show one more of his slides, the one most relevant to the Breakfast Bytes audience, the AI Chip Moonshot Program.

With Taiwan manufacturing some huge percentage of non-memory chips, they inaugurated the Taiwan Semiconductor Research Institute in January of this year, by merging the National Applied Research Laboratories, the National Chip Implementation Center, and the National Nano Device Laboratories. It is based here in Hsinchu and describes itself as an "IDM-lite semiconductor research institute". I assume that means they don't have any fabs and rely on all the existing manufacturing capacity already on the island.

Tracks

The afternoon consisted of six tracks running in parallel:

Track 1 was Digital Full-Flow Design.

Track 2 was the academic track...no, wait, it has to have AI in it...it is the AI Research and Academic Network track.

Track 3 was System Design and Verification.

Track 4 was Custom Analog and Mixed Signal.

Track 5 was PCB Design and System Analysis.

And new this year, Track 6 was IC Design in the Cloud, with presentations from TSMC, AWS, Microsoft Azure, and Cadence's "Mr Cloud" Craig Johnson.

Craig's Five Lessons

Craig went over the Cadence cloud offering, which I have covered as it has evolved, most recently in Cadence Cloud Passport Partner Program. Craig distilled some of the things that we have learned over the last couple of years since we have been working with partners to create our cloud offering. Like the old Letterman top ten lists, it starts from the end, although with only five lessons:

Lesson #5: Companies that find a “catalyst” project make progress more quickly. Don’t pick something where the complexity prevents you learning about the cloud because you are so consumed in the complexity of the project itself.

Lesson #4: Companies solely driven by cost are unlikely to find the cloud very attractive. You can get better results but it may not be cheaper. Also, analysis of total cost of ownership (TCO) needs a very complete view with the full scope of everything, which is not always readily available.

Lesson #3: Companies with top-down directives avoid getting mired in roles and responsibilities debates between design groups, cad groups, and IT.

Lesson #2:  Collaborative engagement with the various partners (Cadence and the cloud vendor in particular) get to a successful conclusion more effectively than “spec and RFP”, since you don't really know what to spec.

Lesson #1: Inertia of the status quo is the single biggest reason cloud becomes a perpetual "future project” to be done next year. 

Craig did say that Cadence is looking at license models as these engagements get bigger. Obviously, if you want to run simulation on 75,000 cores, let alone a million, then "buy 75,000 annual licenses" is not the right model.

Final conclusion:

The time has arrived for IC design in the cloud.

Sign up for Sunday Brunch, the weekly Breakfast Bytes email.