Cadence Certus Closure Solution: Automated Full-Chip Optimization

Today, we announced the Cadence Certus Closure Solution, the first-of-its-kind fully automated environment featuring massively parallel and distributed architecture. It supports design optimization and signoff with unlimited capacity delivering overnight turnaround time. This delivers a 10X productivity increase compared to the manual approach to finalizing design optimization and signoff. This involves the blue wheels in the diagram below. Each run through the wheels takes five to seven days per iteration, and the number of iterations is unpredictable, perhaps as many as 30. Do the math and the whole process at a full-chip level can take as long as three months.

The two main tools are Tempus ECO, used for optimization at the block level. Then Tempus STA for static timing at the level of the whole SoC. What is lacking is full-chip (or subsystem) optimization and signoff. As for things like inter-partition power recovery, that is a luxury that there is simply no time in the schedule to address.

The Cadence Certus Closure Solution automates this whole process leading to overnight optimization and signoff closure. This works by building on top of Tempus Signoff (STA or DSTA), and Tempus ECO in an Innovus flow. The Certus Closure Solution takes advantage of the depth and breadth of our timing and ECO technology.

Of course, the way this is done is to massively distribute all of the tasks and automate the whole process. The diagram below shows how all the pieces fit together. As is usual for a massively parallel system like this, there is a manager that controls what all the worker tasks do, and pulls the results together to decide what needs to be done next.

In addition, inter-partition power recovery can reduce power by 10%-15% and up to 5% for full-chip, something that I mentioned above there is never time to address in the manual flow.

To summarize, the key benefits are:

• Innovative architecture: The Cadence Certus Closure Solution’s Distributed Client Manager supports true, fully automated, and distributed hierarchical optimization and signoff closure at the chip level.
• Improved engineering productivity: It reduces the need for multiple, lengthy iterations across multiple teams, providing a faster path to closure.
• SmartHub interface: The enhanced GUI for interactive and detailed timing debug also allows cross-probing with the GUI to drive last-mile design closure.
• Incremental signoff: This provides 10X improved turnaround time with flexible restore and replacement of only the changed blocks and expends design closure time with an incremental timing refresh.
• 3D-IC design efficiencies: Tightly integrated with the Cadence Integrity 3D-IC Solution, it allows users to close inter-die paths across heterogenous process dies.

Examples

Let's look at a couple of examples.

Example 1: 22M instances in 6nm, ran in 11h (10X improvement). See the diagram above for more details.

Example 2: 140M instances, 16nm, ran in 13h (8X improvement).

Read More

See the Cadence Certus Closure Solution product page.

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