This is a follow on to my previous two pieces about system-in-package (SiP) designs, System in Package, Why Now? Part 1 and Part 2. I'm going to use the term SiP generically just to mean any design with more than one die in the package. The focus of today's post is how you go about designing an SiP. Some of what I'll talk about is applicable even to simpler designs, with a single die in a single package, especially with complex packaging technologies.

First, as you can see in the above picture, there are a number of ways to handle the design:

• Designing the package itself with a mechanical leadframe
• Designing packages with routable organic and ceramic substrates, a PCB-style design flow
• Designing 2.5D silicon interposers, embedded bridges, and fanout wafer-level packaging (FOWLP) a hybrid design flow
• Designing 3D ICs with TSVs (usually) in an IC-like design flow

The next generation of packaging can get even more heterogeneous, with (for example) 3D stacks on a 2.5D silicon interposer, such as in the picture above, itself on an organic interposer with more components.

This type of design leads to a number of challenges:

• Top-level design aggregation and management
  • Pre-layout planning
  • Top-level (chip to chip to package to PCB) netlist definition
  • System-level I/O optimization
• Understanding the right level of chip(let) abstraction/representation
  • Simple (extents and pin locations)
  • Complex (full chip(let))
• Advanced multi-chip(let) IC packages require specialized verification
  • Layout vs schematic (LVS) connectivity validation driven by top-level management tool
  • Advanced chip-to-chip alignment checking
  • Silicon substrate design and verification methodology
• Cross-domain electrical/thermal modeling
  • Modeling the coupling effects between domains?
  • Linking different extraction tools for IC, package, and PCB?

OrbitIO

Implementation and Signoff

Cadence has a lot of well-known tools, such as the Innovus, Allegro, and Virtuoso technologies. One tool that is much less well known is OrbitIO. The reason is that, until recently, complex SiPs were not widely used. OrbitIO is a tool for planning, optimization, and management of this sort of design. It handles the top-level schematic/netlist, and any die stacks.

The actual implementation is then passed off to Cadence's portfolio of implementation tools: Innovus, Virtuoso, and Allegro. There is then a second suite of extraction, verification, and signoff tools: Voltus, Sigrity, Clarity, Celsius, Quantus Extraction, Tempus, Pegasus, and Modus Test.

Which implementation and verification platforms are most appropriate depends on the style of the design, largely whether it is like a PCB (in which case, tools like Allegro and Sigrity are probably the best choice), or whether it is mostly like an IC design (in which case, tools like Innovus and Voltus are probably best). The table above dives down to the next level of detail of the tradeoffs involved.

All the multi-die tools can handle multiple PDKs, since the die often are in different technologies but need to be analyzed together. It is also possible to, for example, to examine (or make changes to) a die by opening Virtuoso on the IC design in the context of the SiP. The databases are shared so that it is not necessary to keep writing out files from one tool and reading them back into another tool. While each tool has unique capabilities, they all also have cross-platform capabilities.

It is impossible in a single blog post to describe the capabilities of all the tools, especially in this context where tools stretch from mechanical modeling, PCB design, IC design, on-chip signal integrity, board- and package-level signal integrity, thermal and electrical modeiing, RF, silicon photonics...in fact, pretty much the entire Cadence portfolio of EDA technologies.

The Disaggregated SoC

The SiP, system in package, is becoming the new SoC, system on chip. This is because they are both approaches to integration, but increasingly it is the SiP that is most cost effective and highest performing. In an SoC, by definition, everything has to be in the same process. This has been the main approach to integration since chips were big enough to include microprocessors along with all the supporting logic. But now, not every logic function needs to be in the same process. There are also moves to standardize chiplet interfaces, which should make building the disaggregated SoC using SiP approaches a lot simpler.

We have been working with partners on 3D-IC for well over a decade. We have completed over 10 test designs, with multiple production tapeouts and SiP designs. Of course, there are ongoing projects, too.

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