Breakfast Bytes Blogs

I was talking to someone at Cadence recently and I was surprised that he didn't know what CMP is. To me, it is one of the most unlikely steps in the manufacture of integrated circuits. CMP stands for chemical-mechanical-polishing or chemical-mechanical-planarization. These are just two different words for the same thing, not two different processes. Given everything that you have heard about the cleanliness of fabs, CMP seems ridiculous. It literally is grinding the wafer down to make it flat, or at least flatter. It sounds more like something that would take place in a metal foundry, not a semiconductor foundry.

There are two reasons for CMP. The first is that there are issues with step coverage as the wafer gets "hillier". The second is that the depth of field for the photolithography step is too small and so some parts of the wafer will be out of focus and so not print correctly unless the wafer is first planarized (flattened).

Here's a picture that shows you how the process works. The wafer is face down (active circuitry down) on the end of the thing that looks a bit like a piston. The platen underneath rotates, and a slurry of an abrasive mixed into a liquid is added to the rotating platen to actually remove the highest points of the wafer.

If you want to dive deeper, you can watch the whole video that I took this screenshot from. It is eight minutes long.

At the recent CadenceLIVE Silicon Valley, Sam Nakagawa of GlobalFoundries was scheduled to present Wafer Scale CMP Modeling. Unfortunately, he couldn't make it and so Tamba Gbondo-Tugbawa presented instead. He is Cadence's expert on the CMP simulation tools that we deliver. No, until that day I didn't know we had CMP simulation tools either. Today, planarization is so important that it is used on almost every layer of the chip, with more being added with each process generation as the number of interconnect layers increases and as the depth-of-field issues become more acute with smaller feature sizes.

The above diagram shows the issues that can arise with CMP. Basically, some areas end up with too much material removed, and some end up with too little removed. This obviously means that the wafer is not perfectly flat. It is perhaps worth explaining that copper interconnect is created with a dual-damascene process. This means that the wafer is prepared and left with "holes" where the copper is required. The copper is deposited and fills these holes, but leaving a lot extra. CMP is then used to remove the extra. A similar process is used for "gate last" HKMG processes where the sacrificial gate is removed, and then the resulting gap is filled with the metal gate material (which is something weird like Hafnium Oxide—who had even heard of Hafnium until the last decade?).

Normally, CMP modeling is done at the die level, since all the die on the wafer are identical, at least in volume manufacturing. A "typical" die is selected, one that is not in the center of the wafer nor right on the edge. The simulation is then used to predict erosion, dishing, surface height, non-uniformity, and other undesirable results of CMP. The diagram above shows this die-level modeling using Pegasus CMP Predictor, Cadence's CMP product. For the "die of interest," the model predicts topography accurately, enables hotspot detection, and changes to the CMP that can be made to address issues.

One limitation of this approach is that it only looks at one die, and die are becoming very large so the assumption that CMP is uniform across the die is not accurate. Pressure is different across different rings on the wafer, the speed varies across the wafer (if you rotate a wafer, the outside is moving faster than the center), and as a result removal rates vary across the wafer. With large chips, it is necessary to take wafer-level effects into account.

To do this, multiple die are selected at different positions on the wafer (center, edge, in-between). Each die selected can then be analyzed separately (at the die level).

There are variations. GF presented several graphs, but here is just one showing that there are differences between the three die at different radii from the center of the wafer. The pattern dependencies vary from die to die, and with greater variability on the upper-level metals (due to the cumulative effect of CMP on many earlier layers).

Summary

• For various reasons, but especially the need for faster training of neural networks, chips are getting larger.
• Predicting the patter-dependent CMP performance on such chips and optimizing the CMP processes used on the time requires an integrated wafer and die level CMP simulator.
• Using Cadence's new integrated wafer-and-die-level CMP simulator, comprehensive predictions of CMP variations and hotspots were successfully made in GlobalFoundries advanced node technology.

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