Bringing Clarity of Signal to High-Performance Connector Design

I recently wrote a white paper on Signal Integrity for 112G, which I'll post about once it is available for general download. I covered a broad range of Cadence technology from 112G SerDes design IP (DIP), to IBIS and AMI models for the channel, to the Clarity 3D Solver for 3D analysis of complex connectors and cables. When I wrote it, I took the connectors as given. The designer mounts them on the board and incorporates them into the signal integrity analysis.

But connectors have to be designed, too. At one level, they are mechanical assemblies of plastic and metal conductors. At another level, they are electromagnetic structures to be analyzed. So I got on the phone with Jason Chan. Today, he works in our hardware verification group but a few years ago he was a connector designer at Amphenol, who is one of the connector leaders with revenue of over $7B. That's a lot of connectors.

Connector Design

Jason told me that connector design is hard, because of the conflicting specifications. As he put it to me:

On the surface when you look at a connector it is really uninteresting. It is just moulded plastic and stamped metal. But with these high-speed ones, they are asking connector companies to design at  low cost but then it also has to perform like an expensive microwave connector.

The connectors need to be designed taking the signal integrity issues into account. Some things simply cannot be fixed up by the equalizers in the SerDes transmitter and receiver. In particular, return loss simply results in less noise margin at the receive since the part of the signal that never makes it to the receiver is obviously not useful during equalization there. Crosstalk, interference between separate signals, is something else that cannot be compensated by equalization since it happens at roughly the same rate as the signal (assuming the aggressor is also running at a similar data rate), too fast for equalizers to adjust and compensate.

The design of connectors has gone through three phases, depending on the amount of compute power available in that phase, and the sophistication of the algorithms for the finite element meshing and analysis.

Connector design is a complex problem, since they need to perform well from a signal loss and crosstalk point of view, yet they are typically manufactured from cheap components, as Jason explained above: plastic and stamped metal. The thing that makes designing connectors for high-speed SerDes so challenging is that they have to be economically manufactured in high volume at a low price—but 112GHz is microwave frequency but without access to expensive and bulky microwave connectors. Actually, because 112G uses PAM-4 signaling, the symbol rate is actually 56 Gsymbols/second, but each symbol conveys two bits (4 values, that's the 4 in PAM4).

For a more in-depth look at PAM4 signaling at 112G, see this video How the Cadence 112G SerDes IP Solves the Challenges of Long-Reach Signaling.

Jason told me how it used to be done:

Let me go back in time. Back in the day when we weren’t so endowed with computer power, we would have to go through a few prototyping cycles. Machine prototype parts, go to the lab, characterize on test boards, measure against design targets. It would take several iterations. As time progressed, we got access to all this compute power and we got all these compute tools. We used a pretty good finite element solver but it wasn’t very robust. It would have problems translating the mechanical model. They made some quantum leaps in “fault tolerant meshing”, a method of overlooking some of the imperfections. That enabled us to accelerate the prototyping cycle, instead of relying on mechancail prototypes. We got it down to one or two prototype cycles. That enabled us to shorten up the time to market cycles from two years to six to eight months.

In this era, the connector would be analyzed separately from the reference board, and then the two sets of measurements combined, on the assumption that there was no electromagnetic interaction between the breakout region of the board, sometimes called “the final inch”, and the connector. At low signal frequencies, the interactions were second order and the errors resulting from ignoring them were small.

For 112G (and 56G) SerDes connections, the signal encoding is PAM4 and high frequency. This already causes challenges before worrying about the connector. The PAM4 loses 9dB versus NRZ. The packages, typically ball-grid arrays, are far from perfect and so already the signal coming out of the package is poor. Jason said that means that the board and system designers often have unrealistic demands:

I want as low as possible return loss, and low as possible crosstalk, but still mechanically small.

The signal rate is 56G symbols per second (or 28G) but higher frequencies also need to get transmitted cleanly to recover the data and clock given the encoding scheme. However, a lot of connectors are mechanical press-fit and electrically large and so not very good. The pins are inevitably close to each other, with no (or limited) shielding. Crosstalk is an especially demanding problem since all the equalizers can do nothing about crosstalk since it is too dynamic. Return loss, essentially energy in the signal that is reflected at the connector and so never makes it to the receiver, is another big issue that the connector designer needs to minimize. Additionally, at these frequencies, the assumption that the connector and board can be analyzed separately and then “added” together is no longer good enough. There is too much interaction between the board and the connector that is not captured in the separate analysis and can no longer be ignored.

Designing Connectors with Clarity 3D Solver

The modern approach to connector design is to use a full 3D analysis tool like the Clarity 3D Solver to do as much of the design as possible “on the computer” instead of by building prototypes. The Clarity 3D Solver, with its ability to take advantage of the huge levels of parallelism available in cloud data centers, can significantly reduce the required wall-clock time for analysis, without compromising accuracy, which is still the first requirement. Getting the wrong answer fast is a poor compromise. The Clarity 3D Solver is also very economical in its use of memory, not requiring any unrealistically large servers.

Of course, eventually, at least one prototype design will need to be manufactured to take real-world measurements, too. This can reduce the connector design cycle to under six months. The Clarity 3D Solver makes it possible to design high-quality connectors and associated reference designs, and predict accurately how they will behave after manufacture. The Clarity 3D Solver scales to large numbers of cores and so it is fast. But, as Jason put it:

Fast is important, but accuracy is even more important

That's the combination that the Clarity 3D Solver delivers.

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