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Every year at the Design Automation Conference (DAC), John Cooley organizes what he calls the DAC Troublemakers' Panel. It used to be called the CEO Panel since the participants were CEOs. Early on, Joe Costello (Cadence's then-CEO) and Gerry Hsu (Avanti! CEO and previously a long-time Cadence executive) got into a literal shouting match. Magma's CEO and Synopsys' CEO refused to be on any panel together. It is always interesting!
This year I expected to see Joe Sawicki, formerly of Mentor, now part of Siemens. But unfortunately, he had a bike accident, got a concussion, and was forbidden to fly, so the Siemens/Mentor slot was taken by Ravi Subramanian, who used to be the CEO of Berkeley Design Automation (BDA) until Mentor acquired it in 2014.
The panel consisted of (from left to right in the above picture):
All questions start with "Q" and were asked by John Cooley. Anything in [brackets] is my commentary.
Q: Ravi, why are you here instead of Joe Sawicki?
Ravi: He had a bike accident, broke a collar bone, had a bad concussion, and his doctor forbade him to fly.
Q: Joe always gets the first question. So you do. Mentor acquired OneSpin just over a year ago. How will you compete with Jasper? Was the acquisition a mistake?
Ravi: Jasper pioneered an app-based focus that expanded the market and enabled a much bigger user base. What we see is that Mentor, through the acquisition of Zero-In, had a solver first approach, but as the market went to app-based approach, we needed specialized apps. OneSpin was growing at 35% per year and growing into various vertical markets. Before the acquisition, Cadence had 55%, Synopsys 20%, OneSpin 25%, and Mentor 13%. The formal market is growing, and we expect to grow our #2 position and take on Jasper.
Q: Dean, you were first on my panel in 2008. Doesn’t everyone already have a design data management (DDM) tool? Why are you here?
Dean: As you know, the EDA market and semiconductors are both growing. DDM [Design Data Management] has expanded significantly. Back in 2008, we were mostly analog. We have since expanded into the digital realm. IP reuse has become huge. In order to keep winning and beating out the competition, we’ve had to drive our tool forward. We were always the fastest tool for DDM out there, but now we are 100X faster. With the geopolitical situation, DDM has got complex. A lot of companies have constraints on who can access what data. It’s a big issue. We’ve had to expand the number of design flows, and covering all of them in a large organization is important.
Q: Since you mentioned the cloud, isn’t that your Achilles heel? Why go to you?
Dean: ICmanage Holodeck is complementary to the major EDA vendors. It improves both naked cloud but also cloudburst. In order to get a workflow into the cloud, a whole load of things needs to happen…and the cloud can get expensive. Here’s some info on Xilinx. In order to speed up tool launch, you need to get all the data to the cloud in order to run it. IC Holodeck only moves exactly the data required. If you are moving 200TB to cloud, it costs a lot. We improve execution performance by optimizing the I/O. We just moved 2TB of the 200TB, so 99% saving. Reduced the runtime from 60 hours to 35 hours, just using caching technology included in Holodeck. In cloud you can pay for a lot of compute, but you don’t always get it due to I/O. It’s all about design data management and getting it in the right place.
Q: Tom, you guys have cloud. Why isn’t Dean out of business?
Tom: We love that people are using the cloud. And this morning we announced the acquisition of Future Facilities. We’re not here to put Dean out of business. But what we are interested in is how do we democratize design so everyone has access to tools.
Q: Ravi, do you guys have cloud stuff?
Ravi: All the three big EDA companies have cloud solutions since customers are asking for it. You can run in our cloud, point tool, batch mode, even our competitors' tools.
Q: Prakash, you’ve been touting some mystery product at this DAC. So what’s going on with Real Intent?
Prakash: It's a product we’ll be releasing shortly, a new product. I'm not going to name it; that’s why it’s a mystery product. This allows customers to create very custom static signoff solutions that cannot be generalized across different design houses. Users provide signoff requirements. It’s still a static timing signoff tool. Effectively users can create custom static signing solutions with this tool. This product was developed in partnership with a large customer, and they used to just have scripts. That would run slowly with no debug environment. So the new product is a combination of all these capabilities with minimal CAD effort.
Dean: Why the secrecy about the name?
Prakash: We are releasing it in a month.
Dean: Who is the big company?
Prakash: I can’t say, obviously. [In case you don't know, many big users of EDA tools forbid any sort of endorsement, either by their own people saying which tools they use or by EDA companies claiming a company as a customer]
Q: Using a mystery product, can I use Spyglass CDC? Is this locking people into your product?
Prakash: This handles requirements that are not met by other tools.
Q: Tony, welcome to the panel. You are AlphaWave's CTO. In four years, AlphaWave went from founding to a miracle IPO. Why are you even working?
Tony: I wasn’t here during that. I just joined recently. I want to see more growth going forward. Connectivity in the datacenter is where we are focused, and 80% of datacenter traffic is within the datacenter. So I’m happy to hear that since we sell datacenter connectivity IP. We focused on DSP-based transceiver architecture from the beginning. A thin analog part and the rest is digital DSP. We will have variants for 50 interfaces by the end of the year, PCI, Ethernet, long reach, short reach, and so on. Plus in all the technology variants 12nm, 7nm, 5nm, and 3nm. It's the right market and the right technology. The truth is it has not been only four years. I worked with the founding team 20 years ago, and this is three companies later.
Q: There are some key technology limits there. How fast can you process data?
Tony: Back when AlphaWave was getting started in 2017, it wasn’t clear if we could use parallel DSP processing and have PPA that renders the AMS transceivers obsolete. Upper frequency is 200 Gbps transceiver this year [presumably 224Gbps since that is the standard].
Q: How do you compete? Just by cutting prices?
Tony: No, it’s all about PPA, not just price. We were TSMC's supplier of the year.
Tom: Customers want bleeding edge, and many of them use TSMC. I’d like to get Tony as a more active customer of my tools.
Q: Prakash, Mentor CDC and Spyglass have been pushing more on static signoff. How do you compete in that environment?
Prakash: Customers continue to put more complex and larger designs and need to keep the same schedule, so we need further development of technology. It is very hard to scale and it requires continuous innovation. Announced new CDC. We are innovative on three dimensions. 30% improvement in capacity, multi-level organization of information for debug, and methodology and innovative use models. We are focused on creating faster and more robust static signoff.
Q: Sam [finally], speaking of being a drain on the EDA customers’ budget. Everyone has PrimeTime, Tempus, etc., already. Why would they look at your tool?
Sam: STA tools will run the constraints, but if the constraints have errors, you’ll have problems and may need respins. We are checking for clocking errors. Two examples. Chip #1 is a huge SoC with 3000 clocks and a good naming convention. The designer has to declare all these clock groups to stop getting an avalanche of false timing errors. It turns out that for one of these 3000 clocks they had used slightly wrong rules, causing an entire group of the chip not to be checked. The silicon didn’t work. They brought in Ausdia’s TimeVision and within hours had detected the problem.
Q: Tom, in 2019, Anirudh [Devgan, now CEO of Cadence] declared war on HFSS by launching Clarity. So what’s happened?
Tom: Clarity launched at the end of 2019. Data we were showing much higher capacity with the same accuracy as HFSS. No need to partition the design. From IP, to chip, to package, to board, all the lines are blurred. That’s what Clarity allows you to do.
Q: Who are your customers?
Tom: We’ve announced some, Mediatek, Renasas, some system companies we can’t name...but we are not talking just a few dozen customers. It's many, many more.
Q: Ravi, how come you guys don’t have a 3DIC flow?
Ravi: We do have a full 3DIC solution. Four parts: be able to do prototyping and planning, actual verification and testing, analysis engines to provide the insights, and finally, make sure designs are manufacturable. Both Cadence and Siemens/Mentor have been in this area for a decade. We’ve combined stuff from our packaging technology along with Calibre, so these are two critical parts. Also brought test in, since the test is fundamental as to whether having a testable solution, to dramatically reduce the test time. Also, Expedition SI, which is a front-end planning solution. It works with both Siemens EDA and Cadence solutions.
Tony: We are designing chiplets, and this is to go beyond the reticle limit or to blend different technologies.
Q: Ravi, roughly six months ago, you launched inPower Bluewave to a giant 3-way fight with Ansys, Cadence Voltus, and Voltus-Fi. Wally used to say you don’t want to be 3rd place.
Ravi: Of course, nobody enters a market to be third, but the analysis needs are breaking the incumbent tools, so there is an opportunity to provide a disruptive change. Especially when there is a lot of digitally controlled analog, tools are breaking. There’s only one tool in the world that can handle this. We are only six months into the market, and we have customers that you’ve written about on DeepChip. On the digital side, Esperanto has a chip with 1000 RISC-V cores. 3.5B instances. You can’t do EMIR with any other tool. The problem has been dramatically changed.
Q: Tom, do you have EMIR tool?
Tom: Yes, we have Voltus and Voltus-FI.
Q: How is it doing?
Tom: We are growing at over 20%.
Dean: I was just going to say 20% of 0 is still zero!
Q: Who do you have for Voltus and Voltus-Fi
Tom: 30% of Virtuoso customers.
Q: Tom, Aart [CEO of Synopsys] has been doing really well in air war for AI. Synopsys AI is even in the New York Times, Forbes, etc. Making it look like they are kicking ass. Don’t you have marketing?
Tom: I’m sure Synopsys is paying a lot of money to get published in the New York Times, and we’d rather invest in R&D.
Q: Doesn’t that impact stock? You’ve got to woo wall street.
Tom: AI is just getting started, and in many ways, now it is being used to dramatically change efficiency. The design space is too large, and we can help optimize without getting trapped in local minima. We can also do what-if analysis. Both on the chip side and chip-package-board.
Q: Dean, what about AI?
Dean: The key to AI is datasets. You have to have data. We do datasets at IC manage. AI is super application-focused. Dog or no-dog. Or 100 different animals. Think about that applied to EDA, we face thousands of different problems, and there will be an AI thing for each problem.
Tom: You need to be careful since data is the customers' data.
Dean: You are telling me customers need to do their own training?
Tom: I’m saying customers own the large datasets. If you want to go across segments, that is their own data.
Q: Ravi, two years ago, Joe [Sawicki, Siemens EDA] offered free licenses for AFS?
Ravi: It depends on how is the price of one product influenced by the price of another product. One is cell characterization, very short run times. Also, long simulations for analog, and post-layout simulation take a dominant share of the simulation cycles. We had 200 AFS customers when we started this, and now they get 5-10X simulation speed, but the demand for licenses is dramatically larger. Layout is the design, so these are simulations sometimes taking days or weeks. 10X makes a week into a day, or a day into lunchtime, and so on.
Tom: So many corners are being looked at right now. You can’t supply enough simulators.
Q: Are you scaling your prices?
Tom: We are seeing exponential growth across the board.
Q: Tom, you had Palladium and Protium, and you leapfrog each other all the time. The one thing you had is unified compile. Are you about to lose to Ravi?
Tom: We walk in the shoes of our customers since we are developing complex hardware with our own products.
Q: Ravi, was buying Atoptech [actually called Avatar by then] a mistake. You will be #3 at best, and a distant #3.
Ravi: You can’t get to #2 without being #3 first. It is brilliant technology. Place and route are one of the markets in EDA where inside you can be inside someone else’s moat. TSMC started certification at 7nm and 5nm, and Samsung too. 14 customers in 12 months that are not legacy users of Atoptech/Avatar.
Q: Innovus is really known. Fusion Compiler is well known.
Ravi: Absolutely. Innovus is there, and customers want a 3rd solution too. They need a robust enough environment for each tool. It is a node-by-node introduction. Each node warrants a completely new solution. What the world has presented is a new opportunity with the physics changing so much.
Q: Charles Shi [Needham] said that in the next 12 months, there will be a recession. What will be the impact on EDA?
Dean: Just look back; semiconductor is either boom or bust. We are in a boom now, but we are slow on the uptake, and then we build too much capacity and be in a bust.
Prakash: I’m not too concerned. There will be some impact, but what our customers are engaged in doesn’t change.
Sam: The product guys don't want to get behind when coming out of the cycle. Nobody wants to come out of the cycle and realize they are two years behind;
Tom: They have to invest.
Q [John]: Thank you.
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