Portable Stimulus and Correct Designs

The title of this post seems pretty generic, after all who wouldn't want correct designs. But actually Correct Designs is the name of a company. They have been working closely with Cadence on PSS, the Accellera Portable Stimulus Standard, and Perspec (officially the Cadence Perspec System Verifier), which you can think of as our implementation of the standard. It is more complicated than that, and if you want more detail then read my post A History of PSS. Sticking to the history theme, here is a very brief history of Correct Designs.

Correct Designs has been around since 1999, and always specialized in design, verification, training, and services. The company is run by a trio: Steve Burchfiel, Kevin Schott, and Will Mitchell. All of them come from IBM, which is a good place to come from since IBM was ahead of the curve in verification compared to the rest of the industry when they were employees there. They developed a close relationship with Verisity, who had the most state-of-the-art verification technology with approaches like constrained random. Correct Designs became a partner of Verisity and delivered a lot of the training for Specman. They developed a tool called Relay, spun it out as its own company called Severity1. When Cadence acquired Verisity in 2005, they also acquired Relay and folded it into vManager.

Recently, I sat down and talked to the three of them about PSS:

PSS/Perspec is an emerging technology where Cadence has a jump start, and also influenced the standard in the same sort of way that Specman/eRM influenced what UVM became. PSS/Perspec is shaping how you approach the verification of complex SoCs by raising the level of abstraction of stimulus creation, not describing the stimulus itself but how it needs to be created. Since systems have gotten so complex, design groups need help verifying a system consisting of lots of blocks, ensuring that the IP is all working correctly together as a system. UVM techniques with virtual sequences would not hold up, given how complex systems have got.

PSS allows you to describe at a very high level the rules by which the stimulus can be created, so it is portable and resuable. Perspec can generate embedded or C-code that calls to SystemVerilog from that level. Already the  maturity of the tool is way ahead of what else you see in the industry.

It won't get adopted by everyone immediately, just like constrained random and coverage driven methodology took time. But people will see it is the right evolutionary path for system verification. Perspec and toolset adoption is going to spread. People are realizing 10X performance improvement once they have the model written. What you create is reusable and able to target all across systems.

The connection to post-silicon is super-important. We see a dynamic where customers are trying to prevent escapes getting out of the door. That's a really bad time in the revenue cycle, not to mention souring customer relationships. The design team needs to help the post-silicon team find the bugs that got missed in bringup. The good news is that they are working together effectively for the first time ever.

Post-silicon testing and debug has historically gone from a standing start, writing similar tests to run in the lab to those used during verification. There was historically almost no re-use in simulation versus the post-silicon testbench. The PSS/Perspec approach can use the same scenario generator to drive the silicon or the RTL.

You see a similar dynamic when asking the design verification team to provide context in which to verify IP. A lot of bugs come from highly configurable designs where it hasn't been possible to test IP in all configurations since you can't anticipate them all.

Correct Designs is working with Cadence to create training classes and lab exercises. Everything will soon be in place for real engagement with customers.

PSS and UVM are complementary. You will still need to do block-level verification, create transactions, and so on. Of course, one of the outputs that PSS can create is code that calls UVM scenarios. PSS is not meant to replace it. At the simulation level you will still need checkers and scoreboards, even if the stimulus comes from PSS. The UVM framework watches over the design, and it's most effective to reuse the UVM BFM rather than duplicate the effort.

Verification planning is a three-legged stool and falls over if any leg is missing: coverage analysis, checking, and stimulus. Historically the goals were encapsulated in the verification plan. Each is considered a coverage goal, checking goal, or stimulus goal. PSS is an entirely new way to describe stimulus goals versus just using plain English as we have traditionally. It now formally captures the stimulus rather than trying to capture in a mixture of a vPlan and some Word documents. The model is what makes it possible to push-button create the test.

Portable Stimulus Standard Status

Accellera formally approved the PSS standard at the start of DAC earlier this year. As they put it on the Accellera Portable Stimulus Working Group page:

On June 26, 2018, the Accellera Board of Directors approved Portable Test and Stimulus 1.0 as an Accellera standard. For more information, read the press release and supporting industry quotes.

You can download a copy of the Accellera Portable Stimulus Standard from their website here. You can find more details on the Perspec System Verifier on the product page.

 

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