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For the last few years at IEDM, Coventor have run an evening panel session looking at some advanced topic. This year the topic was Everything is Under Control: Delivering the Next Five Years of Semiconductor Technology. Coventor was acquired this year by Lam Research. As it happens, Cadence was an early investor through their Telos Venture fund, and I was an investor in Telos through a very old Cadence deferred-compensation scheme, and just last week, when I sat down to write this post, I got a check for a couple of thousand dollars over 15 years later.
The panelists this year were (from left to right in the photo below):
David Fried, Coventor's CTO (now officially Lam Research VP of Computational Products) introduced everyone, and Ed Sperling of Semiconductor Engineering moderated the discussion.
Ed started off wading in at the deep end and asked the panel whether we can really scale down from 10nm to 7nm to 5nm to 3nm and perhaps more. Mark from GF summarized it as "of course it's possible, even if we don't quite know how. It will be the same going forward, not a straight line. We will get there." Richard of Lam thought we were fine to 5nm, we can see the path, and 3nm is a good chance. David of KT recalls reading 30 years ago on why you could never make a device smaller than the wavelength of the light. The bet against optical has been going on for a long time. 3D NAND is another transformation that is amazing we can manufacture. And, putting in a quick plug for his employer, he said: "if you can make them we can measure them." Gary of ASML thought that the challenge was not technology, scaling carries on. The challenge is complexity and cost, not technology.
Ed wondered, especially for logic, whether we really understand the best way forward. Mark said that one challenge paradoxically is that the number of options has expanded. A few generations ago you more or less knew the materials, the structure. Now more work needs to be done to screen down these options. The golden era when the entire industry had a single solution may be ending and we may not all converge. BEOL has some of that already. Shay agreed, that there are almost too many choices of materials. Richard said that one area of huge opportunity is to lower the resistance by getting rid of the barrier, which is highly resistive and is now occupying a lot of space (this was actually the main topic of last year's Coventor panel that you can read about in Coventor Panel on BEOL Challenges). David said that the cycle time from idea to ship is longer so we need to get the metrology earlier to throw away the ideas that don't work quickly (did I mention KT makes metrology?)
Ed switched from logic to memory, and pointed out that NAND has scaled up to 48 layers and wondered where that is going next. Richard was optimistic that there is a path to 256 layers even though there are lots of challenges even to 128. The big challenge is the memory hole etch (did I mention Lam makes etchers?) which is the most challenging etch he has ever seen with a 100:1 aspect ratio. There was a mini-discussion on whether the etch was one stage or multiple, but the conclusion was that sooner or later you have to stack them, but the more you can push the etcher the more you can buy time. Below is a Lam/Coventor animation of building 3D NAND that makes some of this a bit clearer if you are not an expert on just how amazing it is that this many steps ever yields anything:
Sticking to memory, Ed wondered what is next for DRAM. Gary said that we are marching down 1x, 1y, 1z (these are process generations for DRAM) and trying to squeeze another nm. He hasn't seen another device on the horizon to replace DRAM although Crosspoint could have a place. Mark thought it was a matter of time since there is so much work going on on phase-change memory (PCM), Crosspoint (which may or may not be PCM, too) to match current DRAM price/performance and sometimes replace. David said that it will go on until it stops, and noted that 3D NAND would have taken off earlier but 2D got pushed further than anyone thought possible. Shay disagreed, saying that 3D NAND was ready before 2D ran out of gas, but DRAM is not like there. "We don't have anything in the wings." He thinks there are at least two more generations after 1x and we are hearing about 1a. MRAM (magneto-resistive RAM) will come for embedded but is not viable for high density. David said that KT is not seeing a lot of demand for new structures, which I guess means it's DRAM all the way down.
Since Ed had a lot of equipment people on the panel, he fed them a fastball across the plate. Variation is becoming a big problem, he said. In particular, tool-to-tool variation is becoming a first-order effect (this means that it is starting to matter which scanner, which etcher, etc. is used on a wafer). Mark said that the GF approach has been to try and take the process step, tool, whatever, and make the variation as small as possible. "For the longest time we would just bang on chamber matching to get them to match and then realize it is just inherent variation". Shay said that it is a paradigm shift in metrology, and metrology tools have their own variation. To tie it up, it is important to decide what to measure. In the same way that you cannot optimize each manufacturing step separately, you cannot separate metrology from manufacture. Richard pointed out that chamber matching and tool matching has been 0.5nm for close to 20 years, but the pain to get there is now intolerable. Mark said that a foundry like GF has a unique sensitivity since all ASICs don't behave the same way. More and more knobs get added to the tools, but paradoxically each knob is just one more thing that can vary.
Ed wondered where the matching is being done. Tools? Final structure? Processing? Everyone said, "yes, all the above." Shay said that design needs to take some of the burden. "Design is not independent of manufacturing. Some of the scaling involves putting more demands on the designer." Richard agreed, saying "you can't just stick a design on top of the technology after you're done." Mark said that in the foundry world, the end customer is not open to that, although there is some room. Everyone has a waiver review board and it is a business process as much as a technical one as to what we allow that violates the rules.
Ed asked "Do we need to slow things down?" I think everyone on the panel would like to be able to do that, but... "Market pull is insatiable," Mark said. "It's all about time to revenue." Shay said that market pull is insatiable, so you can't get everyone to slow down. "The guy with the solution first gets most of the revenue."
The panel talked about the general roadmap:
Ed threw it to the audience for the last bit of the evening. The first question was how to mitigate the risk. Shay said that you need parallel paths, and we need more collaboration so that together we can make a better offering. After all, tools have to be developed years ahead of time. Mark said that EUV was a good example of this, where GF has parallel paths, as does everyone else. It is increasingly the same for other process choices. "You don't want to screen down too quickly, so need to keep several balls in the air."
Last was a wild question: what do you think will be happening in 2050? What will the wafer diameter be? Will it still be EUV? How many companies will be able to afford a fab? One prediction was that wafer won't get any larger than they are now (which I assume means that 450mm will never happen). Richard said that since computers will design themselves by then, that the question should be directed to Watson (IBM's AI agent). David said that he just read about artificial life the week before so perhaps there will be a human brain on your desktop by then.
With that, David thanked the panel and sent us out into the night fortified only with Coventor/Lam's wine and hors-d'oeuvres.
So, nothing to replace DRAM, but a human brain on your desktop manufactured on 300mm wafers. You read it here first.
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