Never miss a story from Breakfast Bytes. Subscribe for in-depth analysis and articles.
I have been taking a look at TSMC's 3D packaging technologies. From numerous presentations at OIP and the Technology Symposiums, I knew that they had two. CoWoS and InFO and I knew...well, that's about it, to be honest.
CoWoS (and CoWoS-XL, with larger interposers) is the older technology, first in production in 2012. It is based on a silicon interposer, typically built in 65nm or a similar non-leading-edge process. The first and probably most well-known product to use this technology is the Xilinx Ultrascale 3D FPGAs. The first generation of these used four rectangular dies to make up a large square. The second generation was similar but had a 5th die built in a different technology that contained all the high-speed SerDes I/Os. I suspect that for Xilinx, this design was as much a proof-of-concept as anything else, using a part that had such a high retail price (I've heard thousands of dollars) that they didn't really have to care too much about the cost. The other highly publicized design was a module for HiSilicon (Huawei) with two 16nm network processor die and one 28nm die.
Back in DAC 2012, Cadence announced jointly with TSMC a complete design flow for CoWoS designs. The good thing about CoWoS is that it is very high performance, you can mix dies from different processes, and the dies can be huge. It is now a mature approach that yields well. The bad thing is that it is not cheap. So it is targeted at high-performance parts for FPGA, HPC, GPU, and networking where the benefits of high performance and large dies outweigh the costs.
CoWoS stands for chip on wafer on substrate. There are really four steps to its manufacture:
The newer technology, which will enter volume production next year, is called InFO (which stands for integrated fan-out). This is targeted at mobile and thus is at a consumer price point. For the time being, the focus is on adding DRAM to a logic die. InFO's specs are much more modest than CoWoS, as you can see in the comparison chart above. The big difference, the "how do they do that" feature, is that there is no interposer. InFO itself has molding and metal between the logic die and the package I/Os. Note that there isn't a separate package, the metal and the molding compound is the package. How they make this all work is TSMC's secret sauce. The metal pitch is 5um and the lack of substrate doesn't just keep the price down, it keeps the thickness down, which is another care-about since we all like thin phones.
The first application of InFO is simply to use the routing and mold compound to make a sort of just-in-time package for a single die. For some applications, once this gets to volume, this approach will presumably be cheaper than a conventional package.
The big focus, though, is InFO-POP, which also has a DRAM die connected by what TSMC calls TIV for through-InFO-Via. Since smartphone application processors currently have memory in the same package (using wire-bond technology), I wouldn't be at all surprised to see this in phones next year.
In the future there will be Multi-Chip InFO in which multiple dies can be put side by side (more like CoWoS, but lower performance and lower cost). TSMC call this InFO_S.
As I said above, InFO should be in volume production sometime in 2016, but they have test vehicles. The picture below is a sawed cross-section of an InFO die on a PCB.
For years there have been predictions that "next year" will be the year that 3D ICs truly arrive in volume, meaning in millions. The paradox of 3D has been that the cost has been too high to use for high-volume manufacturing, but without high-volume products driving the learning, the costs will never come down.
CoWoS is used in lower volume high-performance markets. The high-volume consumer markets require something that is lower cost and don't need the bleeding-edge performance. There are about 1.5B smartphones shipped per year, so if this technology is used in even just a few models, it will drive the maturity and yield ramp, the costs will come down, and 3D will almost instantly (well, after a decade of work) be a reality.
In the design space, the challenge is that InFO straddles Cadence's Allegro PCB tools and its silicon design tools. Today these worlds have largely been separate apart from a little bit of analysis. There is a disjoint design environment built on two different databases. The physical and electrical signoff is incomplete. So going forward, this packaging technology is going to pull these two worlds together:
But lots has already been accomplished. For InFO PoP (DRAM on logic), the flow is ready with Allegro+PVS providing in-design DRC, electrical signoff for EMI, co-simulation, IR drop, and ESD. For InFO_S (side by side die), the flow should be ready by the end of the year.
If you are truly involved in 3D then you should plan to attend the 3DASIP conference in Redwood City on December 15-17. Cadence's Bill Acito and Brandon Wang are among the speakers in the design tutorial. Doug Yu of TSMC is presenting Simplified High-Performance Integration Technology which I'm guessing is going to be about InFO.