7 Ways to Get the Most out of DAC

DAC, the Design Automation Conference, is coming up. It's Sunday June 24th to Thursday June 28th in San Francisco. But in a slightly new location: Moscone West. The other halls, Moscone North and South, are halfway through a major reconstruction, as you will see if you glance up Howard Street. Moscone West is on the corner of 4th Street and Howard Street, opposite the Metreon.

1. Keynotes

All four keynotes are 9.20-10am in room 3008 (on the third floor).

Monday: Living Products: Building Connected Devices that Learn and Evolve, by Sarah Cooper, GM of IoT for Amazon Web Services (AWS). Sarah has been building IoT devices for 15 years, long before the catchy phrase internet-of-things was... well... a thing.

Tuesday: The Future of Computing: Pushing the Limits of Physics, Architectures & Systems for AI, by Dario Gil, President of AI and IBM Q at IBM Research. Dario heads up IBM's artificial intelligence research, and if that's not enough, also their quantum computing.

Wednesday: A New Golden Age for Computer Architecture: Domain Specific Accelerators and Open RISC-V, by Dave Patterson, of both Google and UC Berkeley. Dave was the inventor of the Berkeley RISC architecture, a key contributor to the RISC-V ISA... and (with John Hennessy) the recipient of this year's Turing Award.

Thursday: Automation vs. Augmentation: Socially Assistive Robotics and the Future of Work, by Maja Matarić of USC. She is a professor of (quite a mixture) Computer Science, Neuroscience, and Pediatrics.

2. Exhibition

Since this hall has lots of floors but a smaller footprint, one change is that the exhibit area is split across two floors. The "anchor tenants" Cadence and Synopsys are on level 1, and Mentor and the DAC pavilion are on level 2. Cadence is in booth 1305, in the unlikely event we are hard to find. The exhibition runs from Monday to Wednesday from 10 am to 6 pm.

Once again we will have the expert bar, where a wide selection of craft beers will... oh wait, it's not that kind of bar. You can meet our experts, who will share information about our products, covering solution segments ranging from low power to mixed signal, advanced node, verification, IP, and signoff. You don't need an appointment, just show up. But not all the experts will be there all the time, so you need to look at the schedule to see when to drop by. I won't reproduce the whole schedule here, but you can find it at Expert Bar Details.

Also, the Cadence Theater will be back with presentations from customers, partners, and Cadence staff. The full schedule is on the Cadence Theater page.

3. Design Infrastructure Alley

For the first time this year, there is Design Infrastructure Alley (on the first floor). Some of the exhibitors are Google, Amazon AWS, Dell EMC, Alibaba, and IBM. So the weather in that part of the exhibit hall will obviously be cloudy. There is even a second pavilion, the Design on Cloud Pavilion. Plus Cadence has a booth in the alley too.

If you want to get up to speed on the status of EDA and the cloud, let me suggest my two posts: The ESD Alliance CEO Panel: Forecast Very Cloudy and CEO Outlook: Cloudy with No Chance of Meatballs.

4. Free Lunches with Extra Chips

Each day Cadence will host a lunch, with a panel session on verification (Monday), Digital Design (Tuesday), and Analog (Wednesday). All three lunches are in the same room, 3002 on level 3 from noon to 1.30pm. Full details are below. They are free, but if you want to attend, you must register. More details, including the panelists once they are announced, are on the Luncheon Page.

Smarter and Faster Verification in the Era of Machine Learning, AI, and Big Data Analytics

Over the past decade, the core engines of functional verification have matured and are constantly improving in core parameters like performance, capacity, and memory footprint. While formal verification, simulation, emulation, and FPGA-based prototyping are the core anchors, the next focus of attention is the verification fabric that makes optimal use of the engines with planning, allocation, metrics tracking. All of which are getting the industry closer to answering the always lingering question of “When am I done verifying?” The next leaps in productivity will utilize advanced analytics of the data created by the core engines. What will fuel these leaps? Will it be smarter management of the engines?

If you want to attend, you must REGISTER.

Monster Chips: Scaling Digital Design into the Next Decade

Modern SoC design has already become an unwieldy compute-intensive beast with multiple bottlenecks threatening tapeout schedules; how must our semiconductor design methodology and philosophies change to meet the next wave of challenges ahead of us in the coming decade? This panel of expert designers, IP providers, and EDA tool vendors will consider the emerging trends of the next 5-10 years and analyze implications and potential solutions to overcoming these imminent challenges.

If you want to attend, you must REGISTER.

Meeting Analog Reliability Challenges Across the Product Life Cycle

As our lives become more interwoven with electronics, the burden of creating designs that meet ever more exacting reliability challenges have become formidable. How reliable your design is could mean the difference between a multi-million dollar recall or leaving a loved one stranded by the side of the road. While digital design style lends itself nicely to “extremes” testing, it is much more difficult on the analog/mixed-signal side to have the time to do the same. Factors leading to failure can be as varied as thermal overstress, device aging, or design abuse. Reliability testing cannot just be a few tests during the final verification step but rather a philosophy that needs to permeate all aspects of the design cycle. In the end, how confident you will be with your design becomes a paramount decision factor in whether to build the design at all.

If you want to attend, you must REGISTER.

5. Straight Talk with Lip-Bu

In the DAC Pavilion, that's on level 2 of the exhibition (not the Cadence level), on Tuesday from 11.30am to 12.15pm. I guess they don't call it a fireside chat anymore since Lip-Bu's chat a couple of years ago was postponed, due to a real fire. Journalist Ed Sperling will interview Lip-Bu Tan, our CEO, on the pavilion stage.

Almost certainly, you will be able to see Lip-Bu on stage again later the same day at...

6. The Denali Party

DAC wouldn't be DAC without Disco Inferno. It is almost 20 years since the Denali party started. If you want to read the whole story, see my post, Party Like It's 1999—How the Denali Party Started. The party is on Tuesday night from 9pm to 1am at Mezzanine (note: not the same location as last time DAC was in San Francisco, Ruby Skye closed last year). Mezzanine is at 444 Jessie Street, which you've probably never heard of unless you live in San Francisco. It is just off Mint Plaza between Mission and Market at 5th.

The Denali party is open to anyone: student, researcher, exhibitor, customer, blogger groupie. If you want to attend, you must REGISTER. But wait, there's more... you also need to come by the Cadence booth before noon on Tuesday and get a wristband. No wristband, no entry. If you don't make it by noon on Tuesday—no wristband for you. You cannot pick up your wristband at the door.

Do you want to know what Disco Inferno will play? That's the great thing about being a disco band, you don't need to update your set list every year. Here's a picture I took last year of one part of their set list. I think I am safe predicting that they will play YMCA again, and we'll all be in the audience doing the letters.

7. Cooley's DAC Troublemaker Panel

Room 3000 on Monday from 3-4pm. Apart from John Cooley, as edgy-question master, and Anirudh, who will represent Cadence, I don't know who will be on the panel yet... you'll just have to show up to find out.

7½. A HOT Party

Yes, we always overdeliver. On Sunday night, from 6-10pm in the level 3 lobby, it is the DAC welcome reception and the Heart of Technology (HOT) event, to benefit the Gary Smith Memorial Scholarship Endowment. More about that in Breakfast Bytes later this week.

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