DATE: Making Fabs Smarter

One of the keynotes at the recent DATE 2021 was local. Or would have been local if DATE had taken place in Grenoble as originally planned. Of course, DATE was virtual and you could watch from anywhere in the world. About the only thing truly European about DATE was the timezone. Being nine hours behind in California made for "interesting" working hours that week. The keynote was by Philippe Magarshack of ST Microelectronics. They are officially headquartered in Geneva, but their biggest operation is a few miles to the north of Grenoble in Crolles. ST's big 300mm fab, just known as "Crolles" is located there. He titled his keynote Cyber-Physical Systems for Industry 4.0: an Industrial Perspective.

Philippe opened with an introduction to ST. It is bigger than you might think, $10.2B in 2020, with 11 manufacturing sites. Its focus is on smart things: smart industry, industrial IoT and 5G, and smart cities. Later, he focused on what ST does itself to make its manufacturing operations "smart", and I'm going to focus on that part of his talk since readers of Breakfast Bytes generally work in the semiconductor ecosystem somewhere.

Cyber-physical systems have electronics at their heart, but they also involve lots of sensors and actuators. These terms can be used in a very general way. A car with automatic emergency braking (AEB) has radar and cameras (sensors) and can activate the brakes to avoid a crash. Increasingly, as in the case of AEB, there is at least some autonomous decision making—your car will brake autonomously if you don't.

The heart of most of ST's work on cyber-physical systems is the STM32, an Arm Cortex-M series family of microprocessors with over 6 billion chips shipped, and with a portfolio of over 1000 different models. These chips also support a wide range of wireless and wired networking standards to communicate with the sensors and actuators.

After talking about other industries, Philippe moved onto the Crolles 300mm fab (there is also a 200mm fab, I believe). It has a capacity of 6,300 wafers per week (about 27,000 wpm). That's a wafer start about every two minutes. The fab generates 3TB of data every day. This data is used for everything from optimization of the shop floor (easy, small amounts of data), to process control and optimization (moderate), to design-for-manufacturing (DFM), which is the hardest, involving huge amounts of data.

The reason DFM is such a challenge is that it involves detecting small signals very early in the manufacturing process so that a lot of wafers are not misprocessed before the problem is addressed. These can involve:

• Advanced defect classification—this used to be done by humans and was slow and inaccurate
• Advanced wafer classification
• Equipment fault detection (before it fails)—this can save tens or hundreds of wafers from being processed incorrectly on faulty
• Mold scrap prevention

The heart of cyber-physical systems is the "digital twin". This is a model in the computer(s) systems of the physical world. This can range from the top level, looking at a whole factory, to modeling an SoC during development so that its interaction with embedded software can be validated pre-silicon. Philippe dug a bit deeper into the Crolles fab. There are about 600 process steps required for each wafer, so cycle time is about a quarter (three months). There are 25 wafers in a lot. But equipment in the fab is grouped by type and so each wafer (actually each lot) makes a long trajectory through the factory, with automated equipment in the roof to move them around. There are 150 of these in the fab, moving 80 tons per day, with each vehicle going 40 kilometers (24 miles) per day. The digital twin of the factory has to know where every piece of equipment is, and where every vehicle is, and so on (center picture). On the right, the digital twin has to manage the priorities for work-in-progress (WiP, sometimes wafers-in-progress since that is the "work" in a fab). These digital twins enable many factory optimizations.

Closer to the world where Cadence operates, digital twins are used during design. In this context, they are sometimes called "virtual twins". At one level, a single SoC can be validated and things like security can be tested. At the system level, multiple systems can be tested together, and faults can be injected, in a way that is not really even possible in the real world. It is similar to Pascal Traverse's point from his keynote, that I wrote about earlier this week in DATE: What Is Single Pilot Operation? Airbus Explains. Pascal pointed out that a pilot only flies the plane for a few minutes on most flights, and most of them (luckily) are boringly uneventful. They do all their real work on the simulator, responding to highly unlikely events so that, if one happens, the response is second-nature. Needless to say, you can't learn how not to crash a plane by crashing them. But you can't learn how to ensure a robot arm cannot hurt an operator, or even crash into another robot arm, in the real world. An advantage of digital twins is that you can destroy them for free.

Philippe's last slide wrapped things up before the live Q&A.

Q&A

Q: What AI hardware needs to be added to the microcontrollers?

Today a lot can be done without specific hardware accelerators. But we are developing a roadmap that will include specific accelerators based on our own architectures. We think we have some secret sauce in terms of low power and understanding of the application. This will come out in next year to year and a half.

Q: The scrap wafer trends you presented are impressive. What about the modeling? How much effort does it take? What tool improvement would you like to see?

In the four examples I showed of data in the fab at equipment level to understand weak signals, on those examples we could make them happen since they have a common characteristic, a single data source (e.g., image of defect). Single-source data we started a year or two ago and probably have two or three more years of that to go. But next step of value-add is when we can combine information from multiple sources. But this is challenging since different sources have different ways to classify and different causes, so they are not easily connected. For example, ATPG creates vectors and we run the vectors and it might be a short or open but does not correlate with the wafer classification tool that is image-based.  About 80% of the effort is in data cleaning, only 20% in the AI algorithms themselves. So data cleaning could definitely be more automatable so is an area to recommend improvement.

Q: How do you ensure equivalence between physical shop floor and digital twin?

The mapping of the position of machines is dynamic, of course. Not only do we have wireless positioning sensors on all the lots in the fab, but we also have a positioning system attached to each piece of equipment to enable checking they are where we think they are. We have had the experience where equipment has been under maintenance and is not where the system thinks it is. What we call “digital shadow” is taking the physical information back into the digital twin.

Q: Are there any real-life examples of attacks on edge AI computations?

Semiconductor is the most capital intensive industry in the world, so it is “exciting” for a hacker to attack fabs, and indeed this has happened a few times. There was an event in Taiwan a couple of years ago where a USB key had been dropped by a hacker and stupidly inserted in a computer inside the fab. More often than not, though, it is social engineering. The weakest link in a security chain is the human, people put USB keys in their PC, leave their badges in bars, and so on.

Q: What about predictability, or lack of it, in edge AI, especially in the systems area?

This is one of the difficulties in AI in general, and at the edge in particular. It is not 100% predictable. Sometimes it doesn't matter. For example, with predictive maintenance, if you are off by 20% then it is not so good but not life-threatening.

Q: Where do you think this is going?

Multiple cyber-physical systems need to be connected in a coherent manner, and we need common semantic layers (especially “defects” which is what we are looking for in our data-driven decision making). So let’s think about data homogeneity all the way from design, down to initial steps in the silicon manufacturing process.

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