Design in a System Context

If you ask pretty much anyone what Cadence does, the first thing they are likely to mention is providing EDA tools for designing chips. But we actually have a much broader portfolio than that, in particular at the higher level where you are designing systems. Of course, systems contain chips. But the focus of this post is not the chip design tools, but the tools and IP focused on putting systems together and verifying that they will work correctly.

I'm not going to focus on it today, but another big trend in building the most advanced systems is to build them out of chiplets. At last year's HOT CHIPS, I would guess that well over half of all the designs presented were based on chiplets. Recently, in San Jose, there was the First Annual Chiplet Summit, which I covered in several posts (with some more to come). See:

• The Chiplet Summit
• Chiplet Summit: Challenges of Chiplet-Based Designs

Another sign of that trend is that Intel Foundry, which has access to Intel's advanced packaging (EMIB and Foveros) is positioning itself as "ushering in the era of the system foundry." Patrick Gelsinger, Intel's CEO, said:

IFS will usher in the era of the systems foundry, marking a paradigm shift as the focus moves from system-on-a-chip to system in a package.

As the level of abstraction moves up from chip to system, to end-market, it becomes much more differentiated. In many ways, all chips are the same and require the same primary set of design tools. But a smartphone has very different requirements from an automotive chip in many dimensions: cost, reliability, lifetime, temperature range, and so on. This means that the portfolio of tools and IP that are important is more dependent on the application.

So let's look at the Cadence portfolio for several different market segments: datacenter, automotive, mobile, and industrial internet-of-things (IIoT). Obviously, there are lots of tools and IP that are applicable to any market. Almost every chip will use Virtuoso at some point for either analog design or chip finishing. Every design will use Xcelium for SystemVerilog simulation. And so on. The focus of today's post is on the tools that are especially applicable to designs in different segments but less applicable to a generic design. That's actually an oxymoron since nobody designs a chip if it is generic, but you know what I mean.

Datacenter

Datacenter designs are the heart of the market segment, usually called HPC, for High-Performance Computing. I see the market as split into several segments:

• x86: Using Intel and AMD parts to build x86-based processors
• Arm: Building Arm-based datacenter chips such as AWS's Gravitorn series, or Ampere's Altra designs
• RISC-V: This is less mature but is coming up fast in everyone's rearview mirror. Using the highest performance out-of-order RISC-V processors to build chips/chiplets for datacenters (for example, Ventana, Esperanto, or Tenstorrent)
• Accelerators, especially for training neural networks. NVIDIA is dominant today, but VCs have funded an extraordinary number of AI startups (many of which will not make it since there are way more than the market can support, but that's a topic for another day)

Cadence has a lot of IP that are foundational in this market:

• Arm ServerReady/SystemVIP
• PCIe 6.0 and derivatives like CCIX and CXL
• UCIe 1.0
• A whole portfolio of memory interfaces that I'll just call xDDRy as shorthand for interfaces like DDR5, LPDDR4, GDDR6, and so on
• Ethernet

I don't think we have any design tools that are specifically for datacenter designs, but we do have some tools that are applicable to high-performance large designs:

• Integrity 3D-IC for chiplet-based designs
• Cerebrus Intelligent Chip Explorer: For getting the physical design of these chips completed faster and with higher quality (PPA)
• The Dynamic Duo, Palladium Z2 and Protium X2: To get complex hardware debugged and software developed
• Helium Virtual and Hybrid Studio: Supports all of x86, Arm, and RISC-V, to enable software development based on a virtual platform
• Xcelium ML and Jasper ML: Adding machine learning to verification to enable the design to be verified in a shorter time
• Clarity 3D solver: For analyzing the high-performance signals through package, PCB, connectors, backplanes, and more
• Celsius Thermal Solver: High-performance chips generate a lot of heat, and you need to make sure it doesn't cause thermal issues
• 6SigmaDCX: Future Facilities' product for modeling thermal at the entire datacenter level, along with physical/thermal models of pretty much anything you might want to put in a datacenter

Automotive

For automotive, we do have tools specifically for the market segment. Well, technically, for any safety-critical application, but automotive towers above all the others:

• Midas Safety Platform: For Functional Safety (FuSa) and compliance with ISO 26262
• Xcelium Fault Simulation: To verify that whatever goes wrong it will get noticed
• Features in the digital full flow for safety, such as creating safety islands isolated from other parts of the design
• Fidelity CFD for the design of fluid flow in and around the vehicle
• Tensilica Processors from HiFi (for infotainment), Vision (for processing camera data), and ConnX (for radar and lidar processing)
• Tensilica Processors. Yes, again, because I want to emphasize compliance with ASIL-D
• The Dynamic Duo: Palladium Z2 and Protium X2, for developing the central decision-making chips and the associated software, which I've seen estimated as 100M loc for autonomy
• Automotive Ethernet with TSN (time-sensitive networking) 

Mobile

Mobile has some special requirements, most obviously radios. The chips are not the biggest or the fastest, but they are very constrained. They have to live in small packages in small enclosures (phones), which makes thermal issues especially important. If we expand our horizon from the smartphone itself to include things like earbuds, the physical constraints are even more severe.

• Celsius Thermal Solver (along with Voltus) for analyzing all the thermal issues
• AWR RF Design for designing radios and antennas
• Virtuoso for analog design for the chips other than the application processor (AP), such as power management, networking, sensors, and so forth
• Tensilica HiFi for high-quality sound processing (audio) and voice-activated functionality

Industrial IoT at the Edge

Industrial IoT is very varied, and so there is nothing I can think of that is essential to every IIoT system (apart from the basic chip-design tools that every chip requires). But a few IP blocks and tools worth calling out are:

• Tensilica Floating Point DSP for low-power AI and machine learning
• Tensilica Vision processors for camera-based applications
• Tensilica AI Platform for decision making
• Xcelium Fault Simulation for the most safety-critical functions (such as keeping human operators safe from robots they are operating in close quarters)
• Ethernet PHY and controller IP (or perhaps AWR RF Design for any applications that use wireless connectivity)
• Cadence's cooperation with Dassault Systèmes for collaboration on systems involving both chips and complex mechanical requirements, complex bills-of-materials (BoMs), and digital twins

Learn More

I should put a huge list of links here to all the tools mentioned above. But you can find any of them easily, in my experience, by searching for "Cadence" plus the name of the tool. For example, searching for "Cadence Celsius" will immediately take you to the Celsius Thermal Solver product page as the first result on the page (and it is not a sponsored link, just what the SEO pros call "organic search").

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