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It's the end of January and that means DesignCon. It is January 29th to 31st in the Santa Clara Convention Center.
Increasingly, the design of high-end PCBs is all about integrity: signal integrity, power integrity, EM integrity, thermal integrity. Further, since all these are inter-related. Temperature affects power, for example, but power affects temperature.
The big change that made signal integrity so important was the switch from parallel interfaces on chips (one pin per signal, or maybe multiplexing a few signals per pin) to serial interfaces (using very high-speed transmission for all the bits of a value, not one pin per bit). This pushed the speeds of the signals up. For example, last October Cadence announced our 7nm 112G serdes IP (see my post The World's First Working 7nm 112G Long Reach SerDes Silicon for details). The imminent DDR5 standard requires modeling the channel (see my post AMI for DDR5 Made Easy for details). For an overview of all the issues, see my post Mechanical, Thermal, EMI, SI, PI: PCB Design Needs Them All.
Cadence will be at booth 711. The focus will be on these areas and the Sigrity family of integrity analysis tools. You will be able to see how to use them for multi-gigabit SerDes analysis, advanced DDR IP and design/analysis tools, automated IBIS-AMI model creation, integrated electronics/photonic design automation, and more. We will also be showing advanced packaging, as well as cross-platform tools, such as working on a chip in the context of the package and board.
We will have an update on the Cadence/Lumerical electronics and photonics co-design automation flow at 1pm on Wednesday, "Shedding the Light on Photonic Design". Cadence ran their first photonics summit and workshop late last year, and I covered that in Diwali, the Hindu Festival of Lights...and Photonics, the Silicon Festival of Light. For more about Lumerical, see my interview with their CTO, James Pond, in my post An Illuminating Chat with Lumerical's CTO.
The short summary of the flow is that you can do a design in Virtuoso where some of the polygons are electrical and some are photonic, and then do a simulation of the entire design, with the electrical being simulated electrically (by Spectre) and the photonics being simulated optically (by Lumerical's INTERCONNECT). Come by and see it all in action.
If you want to dig into more technical detail, Cadence engineers and our customers' engineers are presenting throughout DesignCon. Here is the summary. See our event page for the full details. In the room column below, the letters indicate the ballroom (so A means Ballroom A), and GA3 means Great America 3.
You can register for DesignCon on the DesignCon website. Note that DesignCon is run by UBM, so if you have ever registered for another UBM conference, such as Arm TechCon, you use the same username and password.
More information about Cadence at DesignCon is on our website.
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