DesignCon 2020: SI, PCB, Packaging, Photonics

23 Jan 2020 • 3 minute read

Next Tuesday through Thursday, January 28 to 30, DesignCon 2020 takes place in the Santa Clara Convention Center. it is actually their 25th anniversary. I think of DesignCon as being about everything other than chip design, but increasingly the focus is on very high-performance PCBs and associated signal integrity (SI). And, increasingly, advanced packaging.

Keynotes

On Tuesday, there are bootcamps and tutorials, but the exhibits are not open. There is a keynote at noon, The Future of Fiber Optic Communications: Datacenter and Mobile by Chris Cole of Luminous Computing. He will be covering technical developments that are increasingly driving the replacement of copper by fiber, silicon photonics, and potential future disruptive developments. All the keynotes are in the theater upstairs in the convention center.

On Wednesday, Warren Savage will give the keynote (it seems he is now at the University of Maryland, having sold IPextreme to Silvaco a few years ago) on Design for Security: The Next Frontier of Smart Silicon. Hackers, security, privacy, and other threats all require security to be designed in from the start and to build up from a silicon root-of-trust.

The Thursday keynote goes into space, with Zahir Ali of NASA's Stratospheric Observatory for Infrared Astronomy (SOFIA) talking about Microchips in Space: How Device Design Enables Amazing Astronomy. He will be looking at electronics for observational astronomy, especially cutting-edge imaging.

Exhibits

The exhibits are open on Wednesday and Thursday from 11:00am to 6:00pm. Cadence will be at booth 711 with our portfolio of tools and IP for design and analysis of advanced systems. In particular:

PCB-/package-level signal and power integrity analysis
True 3D electromagnetic field solver for PCB, IC package, and on-/off-chip parasitic extraction
Electrical-thermal co-simulation for system analysis
Cross-domain, multi-chip(let) package design flows 
Advanced GDDR6 solution for AI, ML, and network applications
Solving complex photonic IC challenges using an integrated electronic/photonic design automation (EPDA) environment

There is also a booth theater with presentations every half-hour on Wednesday and Thursday.

Cadence Presentations

We are also running a special tutorial on Tuesday from 1:30pm to 4:30pm in Ballroom A. Gilles Lamant of Cadence, James Pond of Lumerical, and Samir Chaudhry of TowerJazz will present Electronic/Photonic Design for 5G RF Applications (you need a two-day or all-access pass to attend this session and the ones below).

Cadence is giving several presentations on Wednesday and Thursday, too.

Wednesday

8:00am - 8:45pm Ballroom B: IBIS-AMI Back-Channel System Optimization in Practice (Cadence and Marvell)
2:00pm - 2:45pm Ballroom A: Designing Next-Generation Memory Interfaces: Modeling, Analysis, and Tips (Cadence, Socionext, and Micron)
2:50pm - 3:30pm Ballroom A: AI Interposer Power Modeling and HBM Power Noise Prediction Studies (Cadence and Enflame)

Thursday

11:00am - 11:45am Ballroom G: DARPA Organic Interposer Characterization (Cadence, NIST, Boeing, Broadpak)
12:00pm - 12:45pm Ballroom D: Accelerate Interposer Design Efficiency Using Neural Networks and Genetic Algorithms (Cadence, Intel, and Naveid)
2:00pm - 2:45pm Ballroom E: A Novel Design Methodology that Solves Today’s System-Level Analysis Challenges (Cadence and Texas Instruments)

More Details

For details of Cadence activities at DesignCon, see our DesignCon page.

For details on DesignCon in general, see the DesignCon website (including a link for registration). Or watch DesignCon's 30-second publicity video:

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