DesignCon 2023 Preview

Coming up at the end of this month is DesignCon, obviously not to be confused with the Design Automation Conference which will be in July as usual. The focus of DesignCon is more on designing systems, meaning printed circuit boards, advanced packaging, system analysis, thermal analysis, RF design, and more. Their slogan is "where the chip meets the board". DesignCon will be from January 31st to February 2nd at the Santa Clara Convention Center.

Keynotes

There is a keynote every day, which are always worth attending. Note that you are allowed to attend the keynotes on the free expo pass.

On Monday, the keynote is Post-Quantum Cryptography: The Next Decade of Cryptographic Hardware Design presented by Aydin Aysu of the Cybersecurity Research Lab at North Carolina State University.

On Tuesday, the keynote is Enabling Autonomous Robotics Through Electrical Engineering presented by Devin Billings of Boston Dynamics (that is the company, now owned by Hyundai, that makes those amazing videos of robots dancing, doing parkour, and gymnastics. Here's a teaser, this year's holiday video putting a ribbon on top of the Christmas tree:

Then Cadence's Ben Gu will give the keynote on Thursday February 2nd at 10am to 11am in the big upstairs theatre. His presentation is titled The Intelligence to Design Intelligent Machines. The abstract is:

Electronics design is undergoing a revolution as semiconductors are used in more and more market applications. Each has its unique data and workload and requires customized compute and analytics architectures. Advanced semiconductors are implemented in the latest process nodes, in the most complex 3D-ICs, to achieve top performance with more operational flexibility. When the scope is expanded to the full system, complexity further exceeds the traditional siloed engineering teams and methodology. AI is showing promise for addressing the growing complexity, finding optimal design outcomes, and substantially improving overall team productivity. But not all problems are equal. Which are the intelligent system design challenges that AI is best suited for? What impact should be expected from applying AI to these challenges? And what is the frontier of AI solutions for intelligent system design?

It is hard to compete with Boston Dynamics, but here is Ben a few months ago talking about our announcement of Optimality Intelligent System Explorer, Cadence's AI-driven Multiphysics Analysis & Optimization product.

Chiphead Theatre

Inside the exhibit hall, and also free for people on just an exhibit pass, is the Chiphead Theatre. There are presentations regularly throughout the show. One such session is a panel session moderated by Ed Sperling Will AI Ever Replace Engineers? taking place on Wednesday February 1st from 3.15pm to 4pm.

Ben Gu is one of the panelists. The other two panelists are David Pan of UT Austin, Joel Sumner of National Instruments, and Renxin Xia of Untether AI.

Technical Sessions

Cadence is also presenting several times during the technical sessions. You need at least a 2-day pass to attend these.

• Optimal Design & Swift Workflow for Multi-Layer Structures on Wednesday, February 1, 12:15pm presented by Teradyne's Richard Li. Note that you don't have to pay to attend this one if you attend the encore performance in the free education session on Thursday.
• The Influence of EM Field Solver Numerical Solution Space on Measurement Correlation to 50GHz & Beyond on Wednesday, February 1, 3:00pm presented by Kristoffer Sander Skytte, with cc-authors from Wild River.
• 3D Connection Artifacts in PDN Measurements on Thursday, February 2, 9:00am presented by Ethan Koeter of Amazon, and Cadence's Shirin Farrahi and John Philips (and with lots of co-authors).

Educational Sessions

As usual, Cadence has a whole day of technical sessions on Thursday 2nd, all held in Great America Ballroom J:

• Addressing Package/PCB Thermal Challenges by Extending Your Power Integrity Analysis Methodology | Karthick Gopalakrishnan, Cadence | 8:00am PT
• PowerTree-based PDN Analysis, Correlation, and Signoff for AR Systems | Kundan Chand, Meta | 9:00am PT
• When Chips Become 3D Systems. The Challenges of Designing Multi-Chiplet Packages | John Park, Cadence | 11:15am PT
• Encore Presentation: Optimal Design & Swift Workflow for Multi-Layer Structures | Richard Li, Teradyne Inc. | 12:15pm PT
• Envisioning the Future of Power Integrity through the Eyes of Experience | Istvan Novak, Samtec | 2:00pm PT
• Optimizing 3D-IC Power Delivery with Pre-Route System-Level Simulation | Don Pakbaz, Marvell & Jared James, Cadence | 3:00pm PT
• PCIe Rising:The Journey to 64Gb/s and 128Gb/s | Marc Loinaz. Cadence | 4:00pm PT

Learn More

See the Cadence DesignCon event page.

See the DesignCon website.

 

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