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Paul McLellan
Paul McLellan

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microsoft
bayesian optimization
designcon 2022
clarity

Optimal Design of High-Speed Flexible Interconnectors Using Deep Learning

10 Jun 2022 • 4 minute read

 breakfast bytes logoAt the recent DesignCon 2022, Kyle Chen of Microsoft and Suomin Cui of Cadence jointly presented Optimal Design of High-Speed Flexible Interconnectors by Applying DL Optimization and 3D Electromagnetic Solvers. Kyle is an SI/PI engineer for mixed reality (MR) devices at Microsoft. Suomin is a senior software architect here at Cadence. The "3D electromagnetic solver" is Cadence's Clarity 3D Solver. For background on Clarity, see my post Bringing Clarity to System Analysis. What is being described is an early version of the Optimality Intelligent System Explorer (see yesterday's post Optimality Intelligent System Explorer), but since this was before the official announcement of the Optimality Explorer, the product name was not mentioned in the presentation.

3d electromagnetic solvers

The above diagram shows how an electromagnetic solver works. Basically, the design is meshed, and then frequency sweeping is done for many different frequencies using Maxwell's equations. For a deeper dive into the case of Clarity, see my post Under the Hood of Clarity and Celsius Solvers.

The manual approach to doing this is then for the expert designer to use his or her expertise to tweak some variables and rerun Clarity to see if the changes improved things. The approach described in this presentation uses artificial intelligence (AI) to do that tweaking automatically. The designer sets variables to be optimized and also ranges and constraints. One or more objective functions are then defined.

optimization workflow

The automated process will then alter the variables within their ranges and within the constraints to minimize the objective function(s), as in the diagram above. Kyle took a deeper dive into how optimization works. When Stephen Hawking wrote A Brief History of Time, he was told that each equation included in the book would halve the sales. I feel a bit the same way about integral signs and matrix algebra in blog posts. So I'm not going to attempt to provide a detailed explanation.

Micro-Stacked Vias

A multi-layer rigid-flex printed circuit (RFPC) board uses stripline routing in the flex zone. Due to the bending requirement, thin material layers and hatch ground planes are needed for the high-speed routing. The high-density interconnector (HDI) PCB involves blind vias, buried vies, and micro-stacked vias.

micro-stacked viaMicro-stacked vias require non-functional pads on all the transition layers, created with sequential lamination and laser drilling. The initial design uses uniform via pad size (as in the diagram to the right), but these are parameterized with:

  • Radius of pad size on layer x
  • Radius of via barrel
  • Radius of antipad size on layer x
  • Trace width at port y
  • Constraints: the via parameters are not independent and are subject so many manufacturing limitations such as the aspect ratio
  • To simplify things (this will be changed later), solid ground planes are used for via optimization

AI optimization is then used with those parameters with the objective of minimizing the return loss. The first run stopped with the return loss achieved -35db (which took 85-88 trials). The second run stopped at 250 trials and achieved a return loss of almost -40dB within 100 runs, and then started to diverge (for reasons that are not yet understood).

optimized via stackBetter results can be done if even more parameters are provided for optimization. The end result is in the diagram on the right, where the via pad sizes are no longer uniform. After 100 trials, the return loss was below -40dB. The optimal results took 375 trial samples and a return loss of -42.5dB.

Parameterized FPC Differential Pair

The next optimization was flexible printed circuit (FPC) differential pairs, optimizing both the transmission lines, the ground mesh, and the dielectric thickness.

 Again, this is parameterized like the via stack, in this case:

  • Hatch width
  • Hatch spacing
  • Hatch angle
  • Transmission line trace width
  • Transmission line trace pitch
  • Dielectric thickness

Various good solutions were found. It was noted that the AI was working hard to find symmetry to the ground mesh pattern, but this is much more easily taken by adding a symmetry constraint and forcing the mesh to be on a 45° angle. Then a return loss below -30dB is achieved within 100 trial samples.

Summary

The summary of Microsoft's exploration of the design and the presentation itself is that:

  • The optimization is developed to apply to a rigid-flex PCB design on via structure and transmission line
  • A correlation is presented to demonstrate the accuracy of 3D models using simulation from Clarity adopted in this work to a measurement
  • The optimization is then based on correlated RFPC stackup and material data
  • Interactive and mutual learning between machine learning and learning from machines is demonstrated in this work, which may incur novel design methodologies
  • After several optimizations are conducted, an optimization trend is learned, and a new efficient design rule is developed to meet our design target for a differential pair on RFPC.

 

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