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At the recent DesignCon, Cadence's John Park presented Advanced Packaging Trends and Their Impact on EDA Tools. John admitted that there were too many trends to cover so he would focus on some key areas...which, not coincidentally, are also areas where we are actively working to improve the capabilities of Cadence solutions.
John focused on just two areas:
That's a lot of long words, but the basic idea is to put multiple ICs based on different technologies into the same package (that's heterogeneous integration). Except in the most trivial of cases, you need to plan how to do this, and what would be the best way to do it.
Before 1990, we designed a chip, threw it over the wall to a packaging person, who was a mechanical designer, and then threw that over the wall to the board designer. it was very siloed.
Then, in 1989, Motorola announced the ball-grid array (BGA). Now, each package contained a mini-PCB that required routing, power planning, and electrical design. The BGA, along with other surface mount devices (SMD), meant that boards got higher density (both more layers and tighter routing) and became harder to design and analyze.
Then, for the next twenty years, until recently, there were informal co-design flows that broke down the walls partially, with expertise from one domain being involved in the next. However, EDA tools were not in place to look seamlessly across the chip-package-board domains. Handing this got increasingly complex with 1000s of I/Os, bump placement, RDL routing, and more. Package designers ended up spending less than half their time designing packages, and the rest doing planning. The arrival of gigabit-speed serial I/Os made it more complex still, requiring cross-domain power and signal analysis.
Recently, Moore's Law (linear die scaling) has started to run out of steam. In addition, in a leading-edge process, the product volume required to make chip manufacturing economical has increased. This has led to increasing interest in alternative integration approaches, which collectively get grouped under the catchy name "More than Moore."
We have been putting multiple die in different processes into packages for decades, under the name multi-chip modules (MCMs). This was mostly driven by specialist (and low-volume) requirements in the aerospace market. Decades ago, this was driven mostly by leveraging III-V devices where silicon performance was inadequate and so riding Moore's Law was not an option. However, today and in the future, this is driven by integrating chiplets across various nodes (7nm and 28nm say), different technologies (logic, flash, DRAM), and mixed signal (digital and analog die).
Another trend has been the explosion of different devices requiring different PCB form factors. For example, if you are designing a smartwatch, a lot of the constraints on the chips and packages come from the PCB form-factor (which obviously has to fit in the watch case).
This has driven requirements for the two technologies mentioned at the start of this post, which can broadly be characterized as "how do we put this thing together" and "how do we decide what the best thing to put together is in the first place."
Virtuoso System Design Platform is new technology introduced in May 2017. This creates a tightly integrated two-way bridge between the chip domain, and the board/package domain. It ties into implementation, and into electrical analysis, and soon will have power analysis. The flow is top-down for implementation, and bottom-up for analysis. Connectivity and constraints are passed from Virtuoso down into Allegro for implementation of packages and boards. The analysis flow goes the other way, building S-parameters and feeding them back up into the Virtuoso environment, where they can be simulated.
There is a single hierarchical schematic for IC and package-level design. The diagram above shows three chips as designs (one silicon, one gallium arsenide, one gallium nitride) and then all integrated together into a single package. The single schematic serves as golden source for LVS (historically a problem area due to the tedium of checking thousands of connections by hand). The schematic can also include devices (such as discretes) that are outside the package. At the same time, it is possible to push down into each chip all the way to an individual transistor. It is possible to simulate the chips in the package and board environment.
One of the least well-known tools in the Cadence portfolio has to be OrbitIO, which is a tool for cross-domain planning and optimization. It works with chips, interposers, packages, and PCBs. It doesn't do any actual implementation, it feeds into the suite of Cadence's existing implementation tools (Pegasus/PVS, Innovus, Virtuoso, SiP Layout, Allegro). Since this is an area of increasing importance, I don't feel I'm going out on a limb to say that you are going to hear a lot more about OrbitIO in the future than in the past.
Another reason for that is that we are investing more heavily in the is tool. It allows you to capture analog chips, digital chips, packages, PCBs, etc., all onto a single canvas. You can plan and optimize interconnect paths (for example, to optimize the pad-ring based on BGA constraints). As is shown in the above diagram, it can feed information forward to the implementation tools to do the actual routing or whatever. "Expect to hear more about this during 2018", John said.
OrbitIO can handle a wide variety of flows and technologies (any single design is most unlikely to use them all):
The two bullet summary is "Virtuoso System Design Platform" and "OrbitIO".
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