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Photonics is transmitting data through fiber optic cables. As such, photonics is everywhere in datacenters today, and increasingly likely to be in cars and planes. Optical transmission is very attractive since it can support high speeds, the transmission medium is not heavy ("the transmission medium is light" is true in two different ways!) like copper wiring harnesses, and it is largely immune to external inteference from electromagnetic and RF sources.
Siilcon photonics means implementing photonic circuits on "normal" CMOS processes (perhaps with a few extra process steps) so that the electronics are integrated on the same die as the photonic devices (mainly waveguides, receivers, and transmitters). The basic idea is that the electronics are going to be built on such processes anyway, and there has been massive capital investment in fabs to build wafers like that, so the economics are very attractive if you can build the whole thing on the same wafer. So a silicon photonics device has both electrical and optical input and output ports. It is beyond the scope of this presentation, but one obvious issue is how do you package such devices since a conventional package has bumps for electrical connections but is deliberately designed to be opaque to light, and when you are ready to connect up the fiber optic (which may have to be done in the field), how do you make it cheap to build and test the connection?
Since it is a conventional mask-based CMOS lithography-based manufacturing process, we know that the output is going to be polygons for the different layers. The questions then are: How do you design it? How do you specify a design? How do you simulate it? How do you generate the polygons?
At CDNLive Silicon Valley in April, Jonas Fleuckiger of Lumerical talked about the design of silicon photonics. He covered some basics on the structures that I won't repeat here. If you want a working knowledge then look at my post Silicon Photonics in which Cadence distinguished engineer Gilles Lamant gave an introduction to the field. Jonas was actually talking about a three-way partnership between Cadence, Lumerical, and PhoeniX Software to create a working environment for the design of silicon photonics.
What we would like is a mechanism like we have in the semiconductor electrical world where we can go from TCAD models of the process to PDKs that we can use for designing standard cells and other transistor-based structures, and with those the normal IC design flow can get to work. None of that exists yet in the photonic world. The photonic experts are really good at simulating the photonics but in an isolated environment.
There are big differences between simulating an optical signal versus an electrical signal. The challenges are:
In addition, there are all the same challenges that IC design has been facing for years: complexity and the number of components is always going up, design teams are getting larger, the basics are getting more challenging (in the photonics case with more complex modulation formats), IP and re-use is obviously attractive but again depends on some minimal standards. Another reality is that, by and large, the IC designers are not going to be photonic-literate (and vice versa).
The design and analysis of the fundamental optoelectronics building blocks requires various solvers working together:
Once we have done all that we need to extract accurate and calibrated compact models from simulations and measured data for circuit simulation. This allows knowledge to be shared and IP to be reused. This is the photonic PDK.
To put you out of your suspense, the design framework for all this is the Virtuoso environment. Obviously it can handle all the electrical layout and simulation because that is what it was built to do. But it needs to be extended to work with photonics. Firstly, light doesn't like going around sharp bends. At least until you get to RF, electrical signals don't really care. But that means that curvilinear shapes are heavily involved. It can then bring in pre-characterized blocks (PDKs) including compact models for circuit simulation. Just because there is light involved, doesn't mean that we don't need the basics: DRC, LVS, extraction, and back-annotation. Ultimately, the chips need to be manufactured and tested, so there is also a requirement for DFT, DFM, statistical and yield analysis. Here, in one diagram, is how it all fits together:
I won't explain the Cadence block. If you are not familiar with the Virtuoso environment, there is a lot on the Cadence website (Virtuoso has been around for over 25 years, and even survived a period of me running the group in the dim and distant past). Lumerical provides the simulation and component-level design capabilities. PhoeniX Software provides the photonic layout generation with support for the curvilinear layout, creation of waveguides to get the (light) signals around the chip, and more. When I say "curvilinear layout" it sounds like rounding off the sharp corners that we don't care about for normal IC design. But it means truly weird structures:
It only takes a moment's thought to realize that there are clear advantages to combining the efforts of EDA and PDA (photonic design automation) to deliver a complete integrated solution for silicon photonics. There is a lot of base to build on, with nearly four decades of CMOS design automation, and over a decade of optical component design software development.
But just from this short post, it should be obvious that the differences between electrons and photons, and electronics and photonics are a challenge:
Foundries are another partner that needs to be increasingly involved, just as they have had to get more involved in integrated MEMS design. They will need to upgrade their photonics PDK to similar levels of completeness to what we are used to in IC design.