Dream Chip: A Vision for Your Car

Dream Chip is a company based in Germany just outside Hannover. Martin Zeller presented at CDNLive Silicon Valley on A New Computer Vision Processor Chip Design for Automotive ADAS CNN Applications in 22nm FDSOI. That title is long enough already, but you also need to unpack the acronyms. ADAS is advanced driver assistance system, basically a stepping-stone on the way to fully autonomous driving. CNNs are convolutional neural networks, which is the modern way that vision processing is done for recognizing things like traffic signs and pedestrians. FDSOI, usually written FD-SOI, is fully-depleted silicon-on-insulator, which is an alternative technology for FinFET, originally developed by ST Microelectronics at 28nm, and then licensed to both Samsung and GLOBALFOUNDRIES. GLOBALFOUNDRIES took it to 22nm and have a family of processes that they call 22FDX.

(Dream Chip also presented at CDNLive EMEA in Munich earlier this week, but this post is based on the Silicon Valley edition.)

Given all that, Dream Chip sounds like a startup that is making chips for the fast-growing automotive market, but in fact they are 25 years old, (although only called Dream Chip since 2010 when they became independent from Silicon Image). One area they focus on is image processing for automotive, which sounds much more impressive in German: Bildverarbeitung für Fahrerassistenzsysteme.

The chip that they have designed is a proof-of-concept and is not intended for volume production. It processes the raw input from four cameras, performs calculations, and produces an output for display. It can be used for a number of applications:

• Top view display, as if looking down on the car despite the fact that there is no camera up there
• Digital mirrors
• Pedestrian detection
• LED flicker mitigation—one problem with LED lights on cars, as opposed to the old incandescent bulbs, is that they have a short duty cycle flashing dozens of times per second that fools the human eye but not cameras with an even higher frame rate
• Other CNN object detection

The diagram above shows how the functionality is divided up. A53 is an ARM^® Cortex™-A53, VP6 are multiple Tensilica Vision P6 cores, and HW are blocks designed at the RTL level. The verification is done using either full models of the processors, or replacing them with fast models so that a lot of code can be run fast to exercise the rest of the system (and debug the code).

The chip is designed with a fairly traditional Cadence flow. I won't go into the details, but instead I will focus on one area that is different in automotive: ASIL-C. This is "automotive safety integrity level C", which covers how faults are handled. On the chip there is a separate safety processor unit, or SPU. ASIL-C requires that the system can:

• Detect errors (so ECC, parity, redundant logic)
• Memory BIST and logic BIST (which is run multiple times per second during normal operation)
• Voltage and clock monitoring
• Notify of detected error via an external pin or via the CAN bus
• Errors must be latched and the value can be read out after next startup (ideally stored off chip but it is acceptable to clear at power-on reset)
• Fail into a safe state (reset the SoC, or stay in internal reset until reset externally)

The above diagram shows how this is all implemented on the DreamChip system. White is an area of the chip that has no safety requirements, and problems will not be detected. Yellow is the part of the chip with BIST, parity, ECC and other error detection built in. BIST is run every 250ms so there is no guarantee that problems in the yellow areas will be detected faster than this (although some things like parity are faster). The safety island is orange. It contains watchdogs that check that voltage is in range, the processors are running normally, and so on. Errors in the orange blocks themselves are guaranteed to be detected fast, but the processor may not be safe after detecting an issue.

The red area is the inner sanctum. It is a very small part of the logic, but it contains everything in triplicate with majority voting. It is expected to be able to absorb any single event upset (which would affect only one of the triply redundant circuits). The red block is correct in one respect, it is only a very small part of the design. But it is incorrect in that it looks like all the logic is grouped in a single block. Actually, the triply redundant blocks are spread around physically to minimize the chance that a problem could affect more than one of the sub-blocks. The safety processor is configured with fuses to select how it responds to errors. The chip is ready for ISO 26262 certification but that will take another six to nine months of paperwork.

The characteristics of the chip are:

• GLOBALFOUNDRIES 22FDX technology
• 12-track library (that was all that was available, now there is 8-track, too)
• 7.8mm by 8mm
• Flipchip with 1292 bumps 
• Forward body bias
• Up to 1GHz
• 0.8V core and 1.8V I/Os
• 15M instances

There are plans for the future:

• Mixed forward and reverse biasing
• On-chip voltage regulators for bias domains
• Optimization of power management
• Migrate to 12FDX (12nm)
• Functional safety qualification
• Move encryption from AES to eliptic curve
• Capability to cascade chips (4 chips handling 16 cameras)
• Enhance image pipeline to 36 bit, 4K, 60fps

Here is the demo vehicle, with 4 GoPros as the cameras: