Coming up to the big conferences like DAC, I like to do one or more preview posts, both as a service for people who are already going to help them decide what to attend, and also to encourage people in the industry to attend. DVCon is another conference that I always preview. To find out more, I decided to talk to the general chair, Aparna Dey. That's particularly easy since her office is close to mine at Cadence.

DVCon is March 2 to 5 at the DoubleTree in San Jose near the airport.

By the way, another PSA. I'm not sure how many readers of Breakfast Bytes were thinking of attending SEMICON China like I was. I had even booked my airline ticket before the CoronaVirus outbreak. But, even if you live in Shanghai, you still can't go. SEMICON China has been postponed (no new date yet, until the situation becomes clearer). Late-breaking news, MWC Barcelona is canceled for 2020. Even later breaking news, DVCon China has been canceled for this year too.

I asked Aparna how big the conference is this year. She said that on the paper front, they had 160 submissions of which they selected 43 for the main program, and "about 23" (I'm not sure you can say "about" when the answer can't be 22.9) posters. Most of the technical program is presented by user companies, as opposed to EDA companies. Many of the major US companies doing semiconductor design are presenting. Along with keynotes and workshops, the main program is divided up into sessions, covering topics from Automating Verification Solutions, to UVM Strategies, to Verification Potpourri.

The attendance last year was over 1000 people. They expect more this year just based on the fact that more people than last year have registered for the full program at this point. If you don't want to attend the whole program, the panel sessions and the Accellera lunch panel (see below) are free. I will be attending this year, since DVCon does not overlap with embedded world and MWC Barcelona. So look for some posts about the show in the week or two following it.

The exhibits are free, too. Every evening, there's even free beer on the show floor during the evening reception. Another good sign is that the exhibit space sold out and a few booths have to be out in front of the exhibit hall. We are in Booth 604.

This is Aparna's second (and last) year as General Chair. Before, she was in charge of the workshops on Monday and Thursday. She is proud that she stopped them being monopolized by the big EDA vendors, as used to happen, and made it economical for smaller vendors to present.

A Year of Breakfasts 2019

Last year, I created a book with about 25 posts from 2018 and gave it away at various shows during the year. I've done it again. Furthermore, this year I'll be giving it away at DVCon, so come by and pick up a signed copy at the Cadence booth during the social hour each evening, and during lunch on Tuesday and Wednesday. If you are not already signed up for the weekly Sunday Brunch email, then I'll scan your badge and sign you up with no effort on your part. The picture is last year's cover. If you want to find out what this year's looks like, you'll just have to come along and see.

Monday

Monday is a day of workshops (and the exhibits are not open until the evening).

One big development in verification over the last few years has been PSS, the Portable Stimulus Standard. The most recent time when I covered PSS was a presentation from DAC Intel and PSS...and Simics, a Blast from My Past. There is a new version 1.1. On Monday morning, from 9:00am to 12:00pm, Accellera are presenting a workshop Portable Stimulus: What's Coming in 1.1 and What it Means For You. The speakers are mostly (all?) members of the Portable Stimulus Working Group (PSWG):

• Tom Fitzpatrick of Mentor
• Matan Vax of Cadence
• Prabhat Gupta of AMD
• Hillel Miller of Synopsys
• Karthick Gururaj of Vayavya Labs

That is followed by an Accellera lunch including a panel discussion on PSS. Also, Cadence's Alessandra Nardi, Chair of the Functional Safety Proposed Working Group (PWG) will introduce the charter of Accellera's newest PWG. Functional safety is a hugely important area in automotive, but also in other domains such as aerospace and medical.

Accellera is back in the afternoon with a workshop on The Emerging IP Security Assurance Standard, with some of the working group:

• Brent Sherman of Intel
• Ambar Sarkar of NVIDIA
• Adam Sherer of Cadence
• Mike Borza of Synopsys

By the way, there is already a white paper on IP Security Assurance Standard.

After that, Accelera has a final workshop for the day, How HLS and SystemC Are Delivering on the Promise of Design and Verification Productivity. The presenters are:

• Mike Meredith of Cadence
• Stuart Swan of Mentor
• Matt Bone of Intel
• Rangharajan Venkatesan of NVIDIA

In the afternoon, there are also sessions in parallel from smaller companies:

• Vayavya
• Breker
• Verilab
• CircuitSutra

Two smaller companies get their hour and a half in the sun on Thursday afternoon:

• Semifore
• Agnisys

At 5:00pm, the exhibits open and there is a reception on the show floor until 7:00pm.

Tuesday

In the morning, there are parallel sessions on Formal Verification, Portable Stimulus (if you didn't get enough on Monday), and Automating Verification Solutions. That is followed by the poster session.

There is a Cadence-sponsored lunch with a panel discussion on Towards Intelligent System Design with AI-Enabled EDA. The panelists are:

• Brian Choi of Samsung
• Alex Starr of AMD
• Raju Kothandaraman of Intel
• Paul Cunningham of Cadence
• James Hogan of Vista Ventures
• Moderator: Ed Sperling

After lunch, at 1:30pm, Anirudh Devgan, president of Cadence, gives the keynote Artificial Intelligence for Design Automation. Here is an extract from the abstract:

Throughput in functional verification has been the key value for years, and experienced engineers traditionally have been required to guide the journey of a design to successful tapeout. The incorporation of deep learning techniques draws from the skills of many engineers to explore optimal solutions and achieve better PPA results. This talk examines these transformations and highlights how deep learning brings a shift in perspective to functional verification, charting a path beyond current practices towards Intelligent System Design for an AI-enabled future.

In the afternoon, there are sessions on UVM Strategies, Verification Potpourri, and Power-Aware Design and Verification.

The exhibits are open from 2:30pm to 6:00pm. There is a reception from 5:00pm to 6:00pm.

Wednesday

Wednesday opens with a panel session on New Chip Designs Create Tidal Wave of Change. The panelists:

• Adnan Hamid of Breker
• Mark Glasser of Cerebras Systems (see my post HOT CHIPS: The Biggest Chip in the World)
• Simon Davidmann of Imperas
• Ty Garibay of Mythic
• Jim Hogan of Vista Ventures
• Moderator: Brian Bailey

That is followed by parallel sessions on Hybrid Verification, Verification Strategies, and Formal Verification.

Synopsys will buy you lunch and Johannes Stahl will moderate a discussion with industry leaders...but who remains a mystery since they have not been announced yet.

After lunch, there is a panel Predicting the Verification Flow of the Future with panelists:

• Balachandran Rajendran of Dell EMC
• Saad Godil of NVIDIA
• Nasr Ullah of SiFive.
• Stephen Holloway of Dialog Semiconductor
• Alex Starr of AMD
• Moderator: Jean-Marie Brunet 

Later in the afternoon, there are parallel sessions on Predicting the Verification Flow of the Future, Verification Processes and Methodologies, SystyemVerilog Solutions, Reset Domain Challenges.

The exhibits are open from 2:30pm to 6:00pm. There is a reception from 5:00pm to 6:00pm.

Thursday

Start the day with a three-hour Cadence tutorial on Next-Generation Verification for the Era of AI/ML and 5G with presenters (all from Cadence):

• Frank Schirrmeister
• Larry Melling
• Amit Dua
• Moshik Rubin
• Pete Hardee

Part of the abstract:

This tutorial will analyze the requirements of AI, ML, and 5G applications and their impact on the chip verification and software development process, as well as introduce innovative enabling data-driven verification that goes beyond metrics towards efficiency. This tutorial will also introduce how AI/ML are increasing verification productivity in the formal, simulation, emulation, prototyping, debug, VIP, and test automation domains.

Mentor will treat you to lunch and Tom Fitzpatrick will calm you down and talk about Optimizing Time to Bug, Don’t Panic!!!

The exhibits are not open on Thursday. 

More Information

There will be an App for DVCon where you can set up your schedule...but it's not available as I write this. I'll add a note here when it is, but I suspect if you search for "dvcon" on your app store of choice, you'll find it when it is released.

This is the DVCon website including a link for registration.

Also, here is Amelia Dalton's Fish Fry when she interviews Vanessa Cooper, the Technical Program Committee Chair, and gives a sneak preview of this year's DVCon. And a bonus, Cadence's Seena Shankar joins Amelia, too, to discuss the power of cloud computing in EDA

If you are not in the US, you may have your own DVCon coming up later in the year:

• DVCon Europe is 27-28 October in Munich
• DVCon China has been canceled for this year
• I believe there will be a DVCon India in September, but dates don't seem to be finalized

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