DVCon 2021 Preview

DVCon 2021 is coming up March 1 - 4. It is virtual, of course. I said last year that Aparna told me it would be her last year as General Chair and that this year she would be "past chair". But she spoke too soon. Accellera asked Aparna to step in for another year, along with some of the rest of the committee. Back when we both actually worked out of the Cadence office, Aparna's office is literally just on the other side of the back wall of my office. But neither of us have been in the Cadence office in nearly a year, so I set up a video conference with her to find out about what's new for DVCon 2021, apart from the virtual thing.

She started by reminding me that this will be the 33rd DVCon. Verification was very different back in 1988, when the first DVCon presumably took place if my math is correct. Verilog was still proprietary to Cadence. It would be a couple more years before Cadence put Verilog in the public domain with the creation of Open Verilog International (OVI). OVI would merge with VHDL International in 2000 to become Accellera. UVM wasn't standardized until 2011, although its forerunner OVM, and its fore-forerunner, Verisitiy's eRM, existed.

When you look at the agenda, you might wonder what happened to Mentor. After its acquisition by Siemens, Mentor went under the name "Mentor, a Siemens Business". But now it is Siemens EDA.

Keynote

In addition to Aparna being General Chair, Cadence's Paul Cunningham will deliver the keynote on Tuesday, March 2 at 1:00pm. Paul is corporate vice president and general manager of the System Verification Group at Cadence. His keynote is titled Computational Logistics for System and Software Verification. For more background on Paul, see my post ESD Alliance Evening with Paul Cunningham where he was interviewed by Jim Hogan. The keynote is open to anyone, including people with a free exhibit pass.

After the keynote, Accellera will announce this year's Technical Excellence Awards.

The Conference

The best place to see the full agenda is the program grid. This has days across the top and then lists all the parallel sessions down the page.

The main body of the conference consists of:

• 42 papers (from well over 100 submissions) and 14 posters
• 4 tutorials—normally these are three hours long, but that is too long online so they have been shortened this year to two hours.
• 18 short workshops
• Two panels
• Exhibits

Tutorials

Accellera's tutorial on the Portable Stimulus Standard (PSS) opens the conference on Monday morning.

The other three tutorials are on Thursday morning:

• Cadence on Benefits of a Common Methodology for Emulation and Prototyping
• Synopsys on Raising the Verification Bar: Cloud-Based Simulation Increases Verification Efficiency
• Siemens EDA (fka Mentor) on Applying Big Data to Next-Generation Coverage Analysis and Closure

Workshops

Aparna is proud that she has managed to get shorter workshops by smaller companies included in the conference, at a lower cost. The workshops are:

Monday:

• UVM-SystemC Randomization — Updates from the SystemC Verification Working Group (Accellera)
• Getting to Know Accellera’s Emerging Hardware Security Standard: Security Annotation for Electronic Design (Accellera)
• System-Level Power Analysis with IEEE 2416 Power Models (IEEE)
• UVM-AMS: A UVM-Based Analog Verification Standard (Accellera)
• Early Design and Validation of an AI Accelerator’s System-Level Performance Using an HLS Design Methodology (Siemens EDA)
• Functional SoC and Early Firmware Verification Using a Virtual Realization Layer (Breker Verification Systems)
• Harmonizing Hardware and Software—Inside the Engineer’s Head (Semiphore)
• Smarter Verification Management (Cadence)
• Achieving ISO 26262 ASIL Metrics Using Modern Static and Dynamic Failure Mode Fault Analysis (Optima Design Automation)
• Verification Of Functional Safety For An Automotive AI Processor (Veriest)

Thursday:

• RISC-V Based SoC Design, Verification, and Validation in One Hour (Agnisys)
• Functional Debug: Verification and Beyond (Siemens EDA)
• Accelerate Signoff with JasperGold RTL Designer Apps (Cadence)
• Beyond Bug Hunting: Verification Coverage from Safety to Certification (OneSpin)
• Shift Left: Cloud as the Technology Platform to Enable Faster Verification (Google)
• Fast Forward Your Product Launch Using Shift Left - Hardware-Software Co-Design and Co-Verification Using ESL Methodologies (Circuitsutra Technologies)

Panels

Both panels are on Wednesday (and panels are open to anyone, including people with a free exhibit pass).

Verification In The Open-Source Era with SmartDV, Imperas, DARPA, Siemens EDA, Axiomise, and Google, moderated by Brian Bailey.

Chip Design On Cloud—From Pipe Dream to Preeminence? with SiFive, Synopsys, AMD, and Google, moderated by Ann Mutschler.

Conference Format

The conference is virtual, so even though there are a lot of sessions in parallel, you can download them at your own pace. Each session will be followed by a live Q&A. The recordings and slides will be available for replay/download for some time after the conference, too. The best paper award will be given on Wednesday afternoon after the technical sessions have finished.

You can follow DVCon on Facebook and Twitter with the hashtag #DVCON_US.

Registration

The rates for attending DVCon have been reduced a lot. Early bird registration ends on January 31 (Sunday) and is $199 ($190 if your company is a member of Accellera, which it probably is). From next week, registration will be $225 ($215 if your company is an Accellera member). Or the exhibits, keynotes, and panels are all free. You still need to register, but the price is $0.

DVCon 2022

The current plan for next year is to be face-to-face at the DoubleTree Hotel in the first week of March. But with all the obvious caveats.

Learn More (and Attend)

Everything is on the DVCon website. Or don't procrastinate, and click here to register. Rates go up after the weekend.

Sign up for Sunday Brunch, the weekly Breakfast Bytes email.