DVCon 2022 Preview

DVCon 2022 is coming up soon from February 28th to March 3rd. It is entirely virtual. In my preview post last year I said:

The current plan for next year is to be face-to-face at the DoubleTree Hotel in the first week of March.

But Omicron had other ideas and so the pleasures of the DoubleTree will have to wait another year.

Like those guys, often with British accents, selling rotisseries on those strange cable channels, let me start by pointing out some great value options to attend (with my British accent):

• If you are a student, you can get a full conference pass for just $39 (just look at that lovely crispy chicken skin)
• The "exhibits only" pass is free. $0, but the name is wrong, it is not exhibits-only. That pass also gets you into the keynotes, the panels, and the birds of a feather from the Accellera UVM working group. Plus the exhibits, of course (mmm, that chicken is so tender).
• An all access pass is $215, assuming your company is a member of Accellera, which it probably is, or $225 if not.

Note that you will get login credentials for the virtual conference on February 27th.

So having got that over with, what are the reasons to attend?

Vanessa

Well, rather than trying to answer that question myself, I had a zoom call with Vanessa Cooper, this year's conference chair. In her day job, she is a VP at Verilab, a professional services firm focused on verification. I asked her what was new this year. She said the biggest new thing is Gather.Town, which is a virtual tool embedded in the conference platform. Last year, when the conference was all virtual too, people complained that it was too hard to interact with other people. Gather.Town is not just something grafted onto the side of the platform. The poster sessions are in there, the exhibit floor is in there, the press room is in there, and you can have real 1:1 conversations with anyone (although you can create a bubble if you want to have a private conversation). It has been compared to a video game since you can create your own avatar, there are treasure chests where you can win prizes, and even consoles where you can play real video games. 

We are excited about it. Hopefully, it will increase interaction.

Another goal this year is to bring in more academics, especially young students. DVCon is primarily a conference for practitioners. More and more universities are running courses, mostly at the master's level, on verification. The student rate has been set at $39 as I already said. There are a couple of good reasons for students to interact with other attendees. Vanessa summarized it as:

Companies attending are all eagerly trying to hire people so hopefully, students get to learn not just in classroom but from practitioners.

The one upside of being virtual is that it is easy for people from all over the world to attend without needing to fly to San Jose. Having said that, the plan is to have the conference in-person next year.

Keynote

The keynote (on Tuesday) is by Manish Pandey of Synopsys and Carnegie-Mellon University (CMU). It is titled Unleashing AI/ML for Faster Verification Closure.

Design verification is one of the most expensive and time-consuming activities undertaken in electronic system development. Advances in machine learning (ML) algorithms, software and practices in the last few years have given verification engineers a powerful suite of tools to attack this problem. Verification tool builders have leveraged these ML advances to accelerate coverage closure, generate better simulation distributions, and improve core verification algorithms. We will explore how exploiting supervised, unsupervised and reinforcement learning have enabled order of magnitude gains in closure convergence and verification cycle reduction.

Tutorials

On Monday, there are lots of tutorials, some Accellera groups reporting, and some sponsored by individual companies. Let me focus on the Accelera ones.

PSS in the Real World

PSS is the Portable Test and Stimulus Standard (yes, Accellera added "test" but didn't change the acronym). The presenters are:

Tom Fitzpatrick, Siemens EDA
Matan Vax, Cadence Design Systems
Adnan Hamid, Breker Verification Systems
Hillel Miller, Synopsys

FuSa: An Update on the Accellera Functional Safety Standard

This workshop presents an update on the work performed by Accellera’s Functional Safety Working Group over the past year and gives a preview of the white paper the group is planning to publish in 2022. The presenters are:

Alessandra Nardi, Accellera Functional Safety Working Group Chair (and Cadence)
Darren Galpin, Principal Digital Verification Engineer @ Renesas
Vatsa Prahallada, Technical Director, Design Enablement @ NXP Semiconductors

An Overview of Security Annotation for Electronic Design Integration (SA-EDI) Standard

The Accellera IP Security Assurance (IPSA) Working Group was formed in 2018 by a team of security and EDA experts to work on developing a general and portable IP security specification standard to describe the IP security concerns (threat model) and to guide EDA vendors on how to produce security assurance collateral and use it for the automation of security verification. The specification was approved as an Accellera standard for Security Annotation for Electronic Design Integration (SA-EDI) in 2021.

A presentation on the specification will be given by Sohrab Aftabjahani, member of the IP Security Assurance Working Group (and Intel).

UVM-AMS: An Update on the Accellera UVM

This is a workshop, not purely a tutorial.

In this workshop, the WG would share the findings, requirements and ideas collected so far and the next step plan for the standardization and would like to receive feedback from the analog/mixed-signal verification community. The UVM-AMS tutorial will also share the latest standardization and technology developments as (being) published in the Accellera UVM-AMS whitepaper.

The workshop will be led by Tom Fitzpatrick of the  Accellera UVM-AMS Working Group.

Technical Sessions

Tuesday and Wednesday are filled with parallel tracks of technical sessions. A full program grid PDF (about 40 pages long) is available to either view, download, or print. It's too much detail to list all the individual presentations, but here are the topics.

Tuesday

• PSS (portable test and stimulus standard)
• Mixed signal verification
• Memory and cache verification
• Automating stimulus verification
• Formal verification
• Potpourri
• At lunchtime, there is a session sponsored by Cadence and Imperas on Networking

Wednesday

• Regression runtime and debug optimization
• UVM birds of a feather (open to anyone even with an exhibit pass)
• UVM: Knobs and sequences
• Low power and UPF
• Prototyping

Panels

These are all on Wednesday.

The Meeting of the SoC Verification Hidden Dragons

Moderator is Brian Bailey of Semiconductor Engineering. Panelists are:

Mike Chin, Intel
Adnan Hamid, Breker Verification Systems
Balachandran Rajendran, Dell EMC
Ty Gariby, Mythic AI

Going Faster – How to Cope with Shrinking Schedules and Increasing Complexity

Moderator is Eric Decker of Mythic. Panelists are:

Dan Romaine, AMD
Bryan Murdock, Cruise
Jason Sprott, Verilab
Mark Glasser, Cerebras

Tutorials

On Thursday, there are a lot of sponsored workshops. Cadence is doing two.

ML-Driven Verification: A Step Function in Productivity and Throughput

This workshop will guide participants through the myriad of emerging ML applications within various verification tools, demonstrating how this new technology may make their everyday efforts more effective. Participants in this workshop will be provided a perspective on how to employ these new techniques on next generation verification environments, as they continue to drive towards first time silicon success.

This will be presented by:

• Matt Graham, vManager Product Engineering Group Director
• Amit Dua, Sr. Xcelium Product Engineering Group Director
• Daniel Hansson, Principal ML Software Engineer

Leveraging Virtual Platforms to Shift-Left Software Development and System Verification

This workshop uses an example of early firmware development to introduce the participants to the careful planning and implementation needed to build an environment that works for all teams. Key complexities around rapid creation of models with the right balance of functionality, timing and performance are introduced and management techniques are reviewed.

This will be presented by Ross Dickson and Pankaj Kakkar.

Gather.Town

The exhibit hall is coupled with a networking platform called Gather.Town. The DVCon website says:

The addition of Gather.Town will make spending time with attendees just as easy as in real life. Allowing attendees to walk in and out of conversations in a natural and seamless way.

Somehow, nothing online is ever quite as easy as in real life, but I'll suspend disbelief for now and we'll see how it works out at the event. In real life, when I go to something like DVCon, I serendipitously run into dozens of people that I know. Let's see if it really works like that when I visit.

Of course, you can also meet any of the exhibitors (including Cadence).

More Details

You can download a PDF of the complete program grid.

Everything is on the DVCon 2022 website including a link to register. Or just click below:

Oh, and later tonight, in Europe notation, it will be 22:22 22/2/22.

Sign up for Sunday Brunch, the weekly Breakfast Bytes email.

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