The biggest conference on verification is DVCon, which takes place in the San Jose Doubletree Hotel from 25th to the 28th February (yes, the same week as SPIE...and Embedded World...and Mobile World Congress). Verification covers all of simulation, emulation, formal verification, and FPGA prototyping. And also, especially this year, system-level verification using the Portable Stimulus Standard PSS.

If you are not in the US, there are now DVCons in China, India, and Europe too (later in the year). See the end of this post for dates.

PSS Workshop

PSS is the Portable Stimulus Standard, which is a hot topic following Accellera's release of the PSS standard on the first day of DAC last year. For more about that, see my post A History of PSS. On the Monday of DVCon, Cadence's Sharon Rosenberg is running a workshop Going Practical with Portable Testing and Stimulus Standard (PSS) from 3.30pm to 5pm in Pine/Cedar. The workshop is hands-on (using Cadence's Perspec):

• Study practical applications using examples including low-power, coherency, connectivity, stress and performance, multi-IP system use cases, and more.
• Review and be able to understand standard the new language by looking at code snippets, and build intuition for the value provided by the PSS standard.
• Understand the differences between test creation for pre-silicon verification and post-silicon validation.
• Gain a clear appreciation for the interoperability of PSS and UVM and how to reuse tests from IP to SoC.
• Get a real sense of the flows and tools available in the PSS era by observing running demos for scenario creation, coverage and debug.
• Try PSS for yourself, creating scenarios and some modeling in a fun exercise.

Cadence is also presenting several papers on PSS during DVCon—see below for details.

Data-Driven Verification: Lunch and Tutorial

On Wednesday lunchtime from 12pm to 1.15pm in Oak/Cedar, there is a lunch panel Data-Driven Verification: Going Beyond Metrics to Efficiency moderated by Ed Sperling. The panelists are Intel's Hao Chen, UltraSoC's Rupert Baines, Cadence's Ziyad Hannah, and Arm's Mark Conklin. Come along and get a free lunch (if you already have a conference registration) while learning:

• Why data-driven verification will bring productivity improvements
• Where data-driven techniques are already being applied and their impact
• How data-driven verification can impact all verification engines
• What challenges data-driven verification creates for verification management and automation

Then, on Thursday from 8.30am to 11am in the Oak room, Cadence (along with UltraSOC) is running a tutorial on data-driven verification. 

The shrinking time-to-market windows and design complexity growth is the reality we enjoy each day in all segments of electronic design. Structured metric-driven verification has been used to manage these pressures addressing schedule predictability, engineers’ productivity and design quality. In this tutorial, we will show how data-driven enhancements for simulation, formal, emulation and verification management improve productivity. Leveraging the latest data analytics technologies, like machine learning, inside verification tools is delivering measurable improvements in productivity. Examples of real designs (across multiple segments) and results will be used to illustrate the early promise of an even more efficient data-driven verification future.

Papers and Posters

Cadence is also presenting several papers and posters during DVCon.

Tuesday 9am to 10:30am A Coverage-Driven Formal Methodology for Verification Signoff
Tuesday 10:30am to 12pm (Posters) How to Create Reusable Portable Testing and Stimulus Standard VIP and Utilizing Technology Implementation Data in Blended Hardware/Software Power Optimization
Tuesday 3pm to 4:30pm Yikes, Why Is My SystemVerilog So Sloooow?
Wednesday10:30am to 12pm NVME Development and Debug for a 16 x Multicore System
Wednesday 10:30am to 12pm Test Driving PSS for System Low-Power Validation
Wednesday 3pm to 4:30pm Coherency Verification and Deadlock Detection Using Perspec PSS

More Details

For details on what Cadence will be doing, see the Cadence DVCon page.

Here are full details on DVCon and registration.

Other DVCons:

• China (上海/Shanghai) 17th April
• India (Bengaluru/Bangalore) 25-26th September
• Europe (München/Munich) 29-30th October

Sign up for Sunday Brunch, the weekly Breakfast Bytes email.