Dynamic Duo 2: The Sequel

There's a story, probably apocryphal, about a screenwriter pitching a movie in Hollywood. The potential producer says "It looks like a great movie. It's a pity nobody has made it already so we could make the sequel". Given that almost every other movie these days seems to be a sequel to a comic-book movie or Star Wars Episode 47, maybe it's not apocryphal.

I've been talking about the Dynamic Duo for the last year or so. See my posts The Dynamic Duo and Early Firmware Development at Kioxia America. And this morning Cadence announced the sequel: Palladium Z2 Enterprise Emulation and Protium X2 Enterprise Prototyping. You won't be surprised to discover that the two new products are faster and have greater capacity than their predecessors. And they are more exciting than Ironman 17.

Both systems have 2X the capacity and 1.5X the speed of their predecessors, which obviously means that bigger chips can be handled faster. As with all verification, where you are never truly done, this increased performance can either be taken as a shorter verification cycle or more verification in the same time.

We call these two next-generation systems the Dynamic Duo not just because there are two of them, but because they are designed to be used together. The two systems have a unified compiler interface so that a design that compiles for Palladium will compile and run on Protium. It takes longer on Protium, to be sure, since that also involves an FPGA place and route. Ten billion gates take less than ten hours to compile for Palladium Z2, and less than 24 hours for Protium X2. But it is not just the compiler front-end that is common. So are the debug interfaces and testbench content.

SpeedBridge and Virtualization

There are lots of different ways in which Palladium Z2 and Protium X2 can be used, too many to dive into in a single blog post. A typical use case is to use a PC connected with Cadence's hardware SpeedBridge interface. The testbench is run on the PC, the SpeedBridge can be configured as Ethernet, PCIe, USB, and so on. But the testbench can be virtualized. The testbench can run binary code for a non-x86 processor such as Arm, or a virtual implementation of a tester. As an example, this setup could be configured to test a RISC-V processor running application software on top of Linux (virtualized on a PC) connected to a co-processor (being emulated or prototyped) over a PCIe bus.

Under the Hood

Palladium Z2 is just higher performance all around:

• Scales from 8 million gates to 18.4 billion gates
• 1.5X higher performance on emulation than Palladium Z1
• 10X faster waveform generation
• 2X deeper debug trace depth
• 2X faster memory dump and debug upload
• 2X higher bandwidth to the host workstation
• Higher power density by 50%, so lower operating costs
• Up to 144 concurrent users per rack, with advanced job re-allocation

Protium X2 has higher all-around performance than Protium X1:

• Same blade/rack architecture
• Capacity up 2X to 40 million gates to 2,400 million gates (from 1 FPGA to hundreds of FPGAs)
• 50% faster prototyping runtime performance, up to 150MHz maximum performance
• Faster FPGA-FPGA interconnects with high-speed pin multiplexing
• 2X higher debug throughput
• Host interface up to 200Gbps per blade

And transitioning from version 1 to version 2 of the Dynamic Duo is straightforward:

• Same source code for Palladium Z2, Palladium Z1, Protium X2, Protium X1
• Designs that compile on Palladium Z1 and Protium X1 will compile on Palladium Z2 and Protium X2, so easy transition
• Use mode compatibility
• Same MMP, AVIP, SpeedBridge, VirtualBridge, and Virtual Debug on Palladium Z2 and Protium X2

Concurrent Use

Like their predecessors, Palladium Z2 and Protium X2 are built to a standard rack configuration and are intended to be installed inside a data center and accessed from the engineers' desks. Both can handle many designs concurrently, depending on how much capacity the individual designs actually require. The granularity that can be shared is at the individual chip inside the system, and both systems really do scale so that each individual chip can be used in parallel for a different design:

• Palladium Z2 scales from one chip with 8 million gates and can have up to 144 concurrent jobs per rack. Or can scale to 18.4 billion gates per rack if the whole rack is used for a single design. Beyond that, up to 12 racks can be used for a single design and scale all the way to 18.4 billion gates.
• A full rack of Protium X2 contains 60 FPGAs and we do have customers who run 60 jobs in parallel. Since a single FPGA in Protium X2 holds ~40 million gates, these are not "small" designs. Or the whole rack can be used for a single design of 2.4 billion gates. Or, as with Palladium Z2, a large design can be further scaled across several racks.

The Verification Full Flow

There's another sense in which Palladium Z2 and Protiium X2 are a duo. As I said when we announced the Protium X1 in 2019:

Protium FPGA prototyping and Palladium emulation are designed to be used together. When the RTL is not stable, emulation is great for debug. Once the focus switches to bringing up the software and the system, the Protium platform runs faster although with less visibility. They have the same compiler front-end, which makes it easy to transition from emulation to prototyping (once the RTL is starting to be stable), and back again (for full visibility when debugging tough problems).

That basic message hasn't changed. Just that larger designs can be handled (2X capacity for both systems), and runtimes are further reduced (50% faster for both systems).

Palladium Z2 and Protium X2 are part of Cadence's Verification Full Flow, which also includes Xcelium simulation and JasperGold formal tools, along with other verification logistics such as vManager. As it happens, vManager and Xcelium ML were #2a and #2b on John Cooley's survey of 2020 design tools announced a few weeks ago. You can read about that in more detail in my posts DeepChip Best of 2020: vManager and DeepChip Best of 2020: Xcelium ML.

Who's Using Palladium and Protium

Since Palladium Z2 and Protium X2 are new products, they obviously don't yet have a lot of users. But the previous Dynamic Duo does. In fact, 9 of the top 10 hyperscale companies, 12 of the top 15 semiconductor companies, and 4 of the top 5 smartphone/mobile companies are users of Palladium Z1. Similarly, 6 of the top 10 hyperscale companies, 8 of the top 15 semiconductor companies, and 3 of the top 5 smartphone/mobile companies are users of Protium X1.

The press release for the new Dynamic Duo has quotes from some of the customers who have experience with the two new products, and have seen the increases in speed and capacity. Here's what NVIDIA's Narendra Konda, had to say:

The complexity of our high-end graphics and hyperscale designs increases with each generation, while our time-to-market schedules tighten. Using the common front-end flow in the Cadence Palladium Z2 and Protium X2 systems, we are optimizing workload distribution between verification, validation and pre-silicon software bring-up. With twice the useable capacity, 50 percent higher throughput, and faster modular compiler turnaround, we can validate our most sophisticated SoC designs comprehensively and on schedule.

 

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