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A couple of weeks ago was the Persistent Memory Summit. (For more details, see my post Persistent Memory.) Normally, this might be a minority-interest event, but the potential arrival of a new level in the memory/storage hierarchy means that everyone will (maybe) be affected. The generic name for this technology is PCRAM, or phase-change RAM. The memory works by heating the storage element, and either cooling it fast or slowly. If cooled slowly, the element ends up crystalline. If fast, then it ends up amorphous. These have different resistance, and so can store a bit. The non-generic name for the only currently commercialized technology in the space is 3DXpoint, and Intel has its own name, Optane. It is not quite the dream replacement for DRAM, since it is slower, but it is only 500ns versus 70-100ns, so it is close enough: compared to the processor's raw speed, even DRAM is really slow (200 cycles), so this is slower (say 1000 cycles) but still fast enough that the processor can stall while waiting for an access, and let the superscalar nature of the processor find some stuff to do in the meantime.
But 3DXpoint is not the only game in town. At the Summit, Jim Handy and Tom Coughlin presented on MRAM, XPoint, ReRam: Persistent Memory to Propel Tomorrow's Computing Advances. There was also a panel session (just before, as it happens) where Sony, Everspin, and Avalanche presented on their memory technologies, which are in various stages of development and commercialization.
I talked to Jim, who happened to be sitting next to me, and asked him which of the new upcoming memory technologies he thought would dominate in the market. He said he was surprised that nothing has yet been crowned the winner. Although many technologies might find niches in embedded SoCs, true volume means whole fab-sized investments measured in billions of dollars, so probably only one more technology (beside 3DXpoint) is likely to make it.
One piece of evidence for all the technologies still being in the running was a count of papers from IEDM. All of MRAM, PCM, ReRAM, and FRAM were well-represented. The obvious "big guys" are all still participating: Samsung, SK Hynix, Micron, Toshiba, Intel, TSMC, Macronix, and so on. Plus rumors of flash's death have been greatly exaggerated, as Mark Twain apparently said on reading his accidentally published obituary. The table to the right shows the number of papers on each technology (and MRAM had its own conference the day after IEDM with another 10 presentations).
FRAM, which is Ferroelectric RAM, is experiencing a rebirth. Previously the technology used lead (Pb) which is something nobody wants to let in the fab. But then they used to say that about copper, which is the standard material for interconnect today. But the new approach uses Hafnium Oxide, which is already used for HKMG, so that has provoked a resurgence of interest.
One big driver is that planar NAND flash doesn't scale anymore. For dedicated chips it has gone 3D (at 15nm) but that doesn't work for a CMOS logic process. NOR flash doesn't work with FinFET so stopped scaling at 28nm.
The graph above shows how NAND stops scaling, but these new technologies can continue, at least it looks that way.
Another issue is that building very large memories with DRAM requires adding more and more 8Gb DIMMs, which slows down the memory bus. But 128Gb of memory can be added, using XPoint for just a single bus-load. As I said above, it is slower than DRAM but much higher capacity and cheaper.
One specific problem area is the bit selector. Each memory contains some sort of memory element (to store the 0 or 1) and a select device to pick that particular bit for reading (or writing). The best technologies manage to either use the same device as both the selector and the memory element, or at least hide the memory element underneath the selector so that you don't pay twice. If all goes well, the bit density is simply the limitations of the interconnect spacing in the two directions.
Another problem area are "sneak paths" with memories that use resistance to capture the value, which is most of them (Xpoint and ReRAM in particular).
In the diagram above, the select line comes in from the left (marked "select"). The desired value comes out at the bottom (marked "valid"). But the wires are wires and so conduct in both directions. In addition to the valid bit coming out, the signal goes the other way (upwards on the diagram), then through another low resistance bit, and out via other low resistance bits in the pink paths (marked 'sneak"). The selector mechanism needs to be accurate enough to discriminate the valid bit from the sneak bits.
The main contenders for next generation are:
Here's how the first four main contenders work:
PCRam works via a heat cool cycle. If the little programmable volume (that looks like a drop of liquid in the image ot the left) is cooled slowly, it becomes crystalline. If it is cooled slowly, it remains amorphous. Crystalline conducts but amorphous insulates.
MRAM uses spin tunnel torque (STT) and the oxide either tunnels electrons well or not so well. The bit is set and reset through magnetization (see pic to right).
ReRAM has two types, conductive bridge and oxygen vacancy. They work by chemical changes induced in the switching medium that create low resistance paths. One potential advantage of this approach is that it might be possible to hold analog values (in the resistance) and then use them for the weights in neural networks.
FRAM works by having a central atom that can either be up or down, and due to some hysteresis, the atom stays where it is put until it is moved again (see to right).
If you want more details than in this post, Handy and Coughlin have a full report (which they sell) Emerging Memories Poised to Explode.
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