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Last week was the ESD Alliance CEO Outlook. It was hosted by Keysight (fka Agilent fka Hewlett-Packard) who, in addition to providing an auditorium, provided us all with excellent food and drink.
Actually, the meeting started with what was officially the "annual members meeting," which allows members to vote on things. There was actually nothing to vote on, but the legal setup of the ESD Alliance (fka EDAC) requires an annual members' meeting.
Bob Smith, the Executive Director, took the opportunity to update us on various things that the ESD Alliance has been up to.
There are 40 member companies, 62% in the US, 18% in Europe, 18% in China, and 2.5% in Japan.
Other non-event things:
The panel was moderated by Ed Sperling, Editor in Chief of Semiconductor Engineering. The panel consisted of (from left to right in the photo above):
Simon Segars of Arm. You probably know that Simon is no longer the CEO of Arm (see my post January Update). When I accused him of being an impostor on the CEO panel, he told me that at least he was still formally an employee of Arm for a few more days!
Anirudh Devgan, president and CEO of Cadence since last December. See my post The Old Order Changeth: Anirudh Becomes Cadence's CEO Today.
Aki Fujimura, CEO of D2S "a supplier of GPU-acceleration solutions for semiconductor manufacturing".
Niels Fache of Keysight Technologies where he is vice-president and general manager.
Joe Sawicki, of Siemens EDA (fka Mentor) where he is EVP.
In the exposition below, paragraphs marked with "Q" were Ed asking the question (early) or members of the audience asking once we get to the audience Q&A. Anything in [brackets] is commentary from me.
Q: There is a big move towards design for spec, manufacturing for yield, design for context, all very design-specific. How does that affect EDA?
Niels: There is a paradigm shift to design for context, optimizing the whole system including integration challenges. For example, automotive integrating subsystem, system, autonomous drive. So there is much more concern about the bigger context and optimizing end-to-end. So it's good news for EDA with a bunch of opportunities. Models are key to help with accuracy and reduce physical prototyping. But it does require cooperation between EDA companies since it requires cross-cooperation.
Q: Simon, you are dealing with this all the time. What's going on?
Simon: There has always been context. Design for automotive vs design for commercial grade, for example. As the creation of components gets more complex, we need new views, we need proof it is accurate. So this is a continuation of what has been going on.
Q: We are going to see much smaller batches of chips, so we won't be able to do as much verification as in the past. So what changes?
Joe: Verification is no longer about validating the spec but how do you evaluate system performance, including software stacks, sensors, and everything else.
Anirudh: When I was at IBM, we used to talk about domain-specific computing then. It would take 500 people five years to design. Now it is 50 people in six months. 10X times 10X. Of course, we have to keep getting better and better as we have been with IP. Even as the cost of design is going up, if it has enough volume these things are economic. So more and more companies are doing chip design.
Aki: One of the things we do is help the photomask companies. The mask count is going up and up. The manufacturing cost per chip is now lower than the design cost.
Q: When you look at this industry from the '80s on, we figured we could trade with anyone. Now we’ve seen a level of distrust.
Simon; Knotty problem, luckily I’m not CEO anymore. Work today is done where it is most efficient. And we get unbelievable products at an unbelievably low cost. But now I have to optimize for supply chain security, which will result in increased cost. I don’t know how the world is going to deal with that. As consumers, we like cheap stuff. How we deal with spreading the industry around and then duplicating parts, the challenge will be how are we going to deal with the cost.
Q: Also issues about how you can shift certain things to certain companies.
Joe: I have spent four hours a week for the last few months talking to congressmen and senators because we are entering an era when our industry is being used as a strategic lever. This is no way to run a business. Where this lands I don’t know. One of the things that makes EDA work well, no matter how much you complain about our pricing (which I think is incredibly generous), it is low compared to when different regions want to recreate whole industries. It is going to get much worse before the mid-terms.
Niels: As every region is trying to build these local ecosystems, we are looking at billions. There is a tradeoff between building up capacity and operating it, as set against potential supply chain disruption.
Aki: Certain equipment can’t be exported to some places. The inability to use the leading edge is an opportunity for us since countries have to compete with what they have.
Q: Anirudh, if we have two supply chains is that better for EDA or worse?
Anirudh: I’m more optimistic than previous speakers. If we look at China, for example, we had some companies added to the entity list a couple of years ago, but the three-year CAGR is 20% or so for Cadence in China. We see that continuing in the future. More system companies are doing chip design. There is some local competition, but that’s normal. If you step back and look at aggregated growth, I think it looks good.
Q: Mainframes, minicomputers, to smartphones. Today everything has a chip in there for computing. We are now seeing double ordering, allocation. What does that mean for EDA? We always thought EDA was recession-proof.
Anirudh: I think it is true more than ever. I went to buy a boom-box for $99. And then there was a plastic step next to it so you could work out and it was $149. I don’t think semiconductors ever got the value they deserved. It is expected to double to $1T in the coming years. System companies doing design, that’s not going to stop. At Cadence, we are doing more in the system space, which is growing. These three megatrends are very positive.
Niels: I agree, the near term is challenging. Demand versus supply, so we are adding capacity in 18-24 months. There is a cycle of growth, new logos, more design starts, vibrant market, they all need to tool up, they need IP, they need consulting services. We are in a good place.
Joe: I was presenting to Siemens AG about why our business is so strong. Everyone remembers the doomsaying that no one would design at 90nm, but design starts are increasing at all nodes.
Q: Moore’s Law is being supplemented with more die in a package. What’s the outlook for advanced packaging? Everyone turns to the EDA guy and says it’s all your fault. What’s the impact?
Anirudh: Another megatrend. In 1997, my advisor Ron Rohrer told me SiP would overtake SoC. It has so many advantages. But Moore’s Law will still go for another 5-10 years, the technology scaling part anyway. Needs are driven by system performance and integration. Moore's Law is a natural extension of that.
Aki: The [NVIDIA] Hopper H100 has 17,000 GPU cores in it, whereas the A100 had 7,000. So I take issue with Moore’s Law slowing down. It is scaling in different ways. Not clock speed. But you are able to compute a lot more on one chip. Investment dollars will continue to be available, lithography will continue to scale, it’s just going to be really expensive. There is an insatiable demand for compute, driven by things like AI where you use “brute force” and just go for it and forget half is just wasted.
Simon; I’m a big fan of more computing! Some of these IoT devices are so advanced they use superscalar processors. 3D-IC adds another dimension or two. But it’s not more of the same. You need to solve different problems. Most chips the wafer comes out, the die get sliced up, it goes somewhere. Now you have different die built in different factories. It is very expensive and only a few companies can afford it. So driving the cost out is the big thing, to make it become mainstream. Then it will ignite.
Joe: Anirudh and I finally agree on something! Dennard scaling is dead but Moore’s Law is fine. With 3D-IC we need design-system co-optimization and new tools are starting to emerge.
Q: Anirudh, I know you agree, too.
Anirudh: Of course. We need more challenges to solve. Interface IP between the chiplets, more problems to solve.
Q: Chiplets are an interesting idea with designs from AMD, Intel, and others. Does this model work as well in a commercial marketplace where nobody owns all the pieces?
Simon: At some level, it is just another way to deliver IP, get more reuse, and drive costs down. If you have a processor needed for many markets, you can stamp that out and amortize it. You can mix and match things. I think this will happen. Not for all markets, I don't think it wlll scale down to 50c microprocessor, at least not for a long time.
Anirudh: Groups like packaging used to be a four-letter word but now groups are coming together. The platform allows these things to play well. Need a platform that can do multi-chip, advanced packaging, along with analysis. This is great for EDA, IP, and the foundry business. We talked a lot about design, but another part is verification. Including software. We have hardware platforms for emulation and prototyping. Verification is super critical to the overall design.
Aki: Lots of things that need to be considered as an integrated whole and the big companies are doing that, but the smaller companies are struggling. You need chiplets when you have multiple technologies that you need to combine. Or when high-performance is the thing you want to do and they use a full reticle but that is not enough, they need interposers, memory on the side, and 3D packaging on top of a full reticle design. 3D is happening inside the chip too, 3D NAND with 128 layers, Even the transistors are 3D with FinFETs and now GAA. They are talking about DRAM becoming 3D at some point in the future. Cray computers used to have pods arranged in a circle to minimize the number of wires and make them more uniform. The same thing is happening at nm, um, and even mm. Minimizing interconnect is the key. If you stack chips so memory is on top, it is better than on the side.
Joe: One ironic note, with the supply chain being messed up, having five parts needing to show up at the same time is an interesting challenge.
Q: Chips today are supposed to last longer and be more reliable. How does EDA handle making chips more reliable when they don’t know how they are going to be used in the real world?
Joe: Test really hard. Failures are sometimes due to the fault model. We will have on-chip monitoring to do debug. Aspects of safety and security that need to be done. But it is hitting across all the tools. It is ubiquitous.
Niels: For us, design for reliability is a big thing since we design equipment. You go to a customer and you see Keysight equipment, but also Agilent [Keysight was created when Agilent was split in 2014], and even stuff with an HP logo [Agilent was created when HP was split in 1999, so any equipment with an HP logo is over 20 years old]. We’ve made lot of upgrades to our product lifecycle. Some of our instruments have thousands of components and have to work with hostile temperature, humidity, and air quality.
Aki: In manufacturing, stuff has to last a long time. Some mask makers are using equipment built before Google was formed in 1998. It is actually the case that chips are incredibly reliable. The worst thing is power supplies, the second worse is fans.
Anirudh: We have companies doing software bringup before RTL is finalized, which really helps reliability.
Simon: One thing that’s interesting is these things are much more common than before. We used to be making consumer products, and reliability was not an issue. You’re going to upgrade it before it breaks. IoT devices may be cheap, but you really don’t want to have to go and service them all. Across the spectrum, reliability and security are everywhere, whereas you didn’t have to worry about either of them before.
Q; What about systems and how to debug failures?
Anirudh: Buy Palladium and Protium!
Joe: It's taken a lot of effort, and we are not unique, to communize the compiler and debug environments. I wouldn’t call it a solved problem but we have made big strides.
Q: It is good to see everyone going to the cloud, but how are you going to ensure people can use mix-and-match tools?
Joe: You have to have interoperability in the cloud. But I don’t see people working in walled gardens.
Anirudh: Cloud can mean a lot of things…like AI. We have customer-managed clouds and where we manage the cloud. Some of the bigger companies have huge data centers but are also using the cloud, too.
Q: Are you concerned about the training of the EDA industry, we are the brains and we all have grey hair?
Niels: It's not just a problem for EDA, other aspects of our business, too. So we continue to bring in new blood. We have a good pipeline of new talent in engineering and computer science so I’m optimistic.
Aki: Our people are so good that EDA was targeted by recruiters as people who know scientific computing and all the math. EDA is one place where they all are. All the interest in deep learning is getting to the point that college students are once again interested in scientific computing pursuits. My 10-year-old son is learning Tensorflow.
Simon: Semiconductor is getting a lot of attention at the moment, and as business leaders we need to be engaged with universities and professors. It would be great if there were 1000 resumes for each opening.
Anirudh: Talent is the primary thing. Undergrad and grad. US and non-US. It is big that there are lots of engineers in India and China. Lots of undergrad in AI etc. But if you look at grad education in US, it has has gone down. Reason? When I went to grad school there was lots of industry funding from the likes of Intel, SRC, IBM. Faculty today say it is more difficult to get funding than before. MIT, Stanford, Berkeley, CMU that’s what they all find. As the US government invests back in semiconductors they should not just invest back in manufacturing. Good to see that $13B is for R&D.
Q: You mentioned chiplets and reliability. Are the people who need good reliability going to use chiplets?
Anirudh: There are big advantages in chiplets. There is a need for standardization, but if you have a design with four chiplets you can design a next-generation product with only one chiplet redesigned. Even if you do SoC integration and you redesign one quarter you still need to verify the whole thing. But I think chiplets will be everywhere.
And with that, Ed thanked the panel and we all went out into the night.
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