The ESD Alliance (and, before that, its forerunner EDAC) runs a CEO Outlook panel one evening every spring. Originally, it was focused on the CEOs of the big EDA companies giving an outlook, but since one of them was always in its quiet period, and the others' legal departments pretty much told them they could only talk about the past, that didn't work too well. The format changed to involve more smaller EDA, and IP companies, too. This year, now that the ESD Alliance is part of SEMI, the format changed again. As I said in my recent post Bob Smith on ESD Alliance, ES Design West...with Wine Bob Smith decided to broaden the discussion to cover more of the supply chain than just design and IP. The ESD Alliance also sponsored the evening, providing dinner and not requiring any registration fee.

This year, the panelists were (from left to right in the above photo):

• Jack Harding, CEO of eSilicon (and CEO of Cadence in his previous job)
• Wally Rhines, CEO emeritus of Mentor Graphics (a Siemens Company)
• John Chong, VP of Product and Business Development for Kionix. I'll call him JohnC
• John Kibarian, CEO of PDF Solutions. I'll call him JohnK

The moderator was Ed Sperling of Semiconductor Engineering.

Leading-Edge Nodes

Ed opened the evening by asking about how things are changing as we move to 7nm and 5nm, but the performance and cost benefits are all changing. "What's the next step?"

Q: Very leading edge. most of the biz there, pushing down to the next node. As we move to 7nm, 5nm, the price performance cost benefits are all changing. so what’s the next step.

Jack: We are making 7nm chips and have started 5nm development. The challenge is to find the customer that has enough business to justify $25-30M. It's not for the faint of heart. The notion that someone might dabble and see if it sticks has gone. These are existential discussions for most companies. Designs starts are dropping off so we are looking at re-use by things like chiplets. Decisions made today are led by consideration of how to create the chip at the most reasonable cost, which has caused us to do things we've never considered before.

Wally? TSMC says that 25% of their revenue comes from 7nm, so that game is not going away, and it will remain a vibrant part of the business. But there is also a shortage of 200mm equipment as people revisit older nodes. You can achieve performance goals in other ways than just smaller feature sizes. "The cost per transistor will go down every year for the rest of our lives."

JohnK: "Everyone here is old, so the rest of our lives isn't that long, Wally!" But Denard scaling and clock rate scaling has stopped. There have been a few discontinuous jumps: HKMG, FinFET, GAA. They come infrequently but we need to deliver benefits to the world anyway. This requires more innovation since you can't get it the easy way, through scaling, any more.

JohnC: I agree. As a sensor maker, we are not at all leading edge. Generally 1+um. Our ASICs are mixed-signal so often 130nm (0.13um) or so. However, the easy way to get better economics have hit a wall. 450mm never happened. Line widths are hitting a wall. So we need more creative ways to get performance.

Wally: In my TI days, in the first five years of a node, you did 50% of the lifetime business. At 130nm, the first five years were just 30% and it's been that way ever since.

Jack: In my first month on the job at Zycad, I went to the applied physics lab at Johns Hopkins and some guys at GE announced they were leaving industry since there would be no way to build a chip after 1um. We are constantly finding breakthroughs. But there is an economic reality.

Ed wondered if the market is fragmenting into a lot of niches?

Jack admitted that eSilicon can't make money in older nodes since there are too many small low-margin companies around the world who only need 20% gross margin to survive. As a result, they moved up to bleeding-edge FinFET so that they are not competing with small Asian companies.

Wally: For EDA, it's a great business. They do a good business adding OPC to older node parts. New companies are coming in all the time using archaic design rules but they still need software. A slew of companies have joined the business of chips who never did before: Google, Facebook, Amazon. They are doing chips, boards, everything. Plus about 800 autonomous driving companies. Most will not survive but in the meantime they will buy al lot of EDA software.

Chiplets

Ed moved onto heterogeneous SoCs, not just one processor with lots of cores. "There's lots of stuff with CPU, GPU, DSP, eFPGA, you name it. What are the challenges?"

Jack: It's not so much a chip we are making as a system. Central processor, interposer, HBM. These interposers are mini-PCBs. Supply chain management is a big deal. The first chips we did were painful. The biggest thing that we did was to spend a massive amount of time with our supply chain.

JohnK: Scaling down doesn't give you the density that you need. Chiplets are pushing technology risk back onto the chip companies who have become system companies. Managing analytics, in particular, the known-good-die (KGD) issue, has been a big part of our business.

JohnC: In MEMS, we’ve struggled with standardization. Everything is system-in-package. Devices are links to the physical world so thing like temperature affect it. We still haven’t managed to get a standardized process and toolset for MEMS.

JohnK: Look at microphones or IR sensors. They are incredibly complex with 13 chiplets in that sensor alone. Prices are coming way down. I’ve started wondering why anyone would develop BCD processes any more to put it on the same piece of silicon. Why not just split the DMOS off onto its own chiplet. There will be a lot more innovation.

Ed wondered about IP. "It's a black box, but now you have to fit it into tight constraints with thermal, EM, etc. If something is burning up, it will burn the whole chip."

JohnK: If you look at 7nm models from a foundry, they’ll give you a different SPICE model for each package. This is because they will thin the die differently. It can pass wafer sort and when we put it in the package, it no longer works. So we need more sensors on-chip for temperature, process, etc. to read it out in the field. It behaves so differently at wafer sort from in the package.

Jack: "Pretty much every chip we make has high-performance SerDes on it. I see us moving to chiplets for stuff that is analog, doesn’t scale, and where there is no benefit from having it integrated."

JohnK: "You want to give more compute to the TPU or whatever, so you want to kick everything else off the die. It delivers more benefit at the system/architectural level. You want to deliver something else or you want to use all the leading-edge silicon for differentiation." He pointed out that the number of people doing full 8 square centimeter full-reticle chips used to be low, but now there are startups that fill the reticle and then put everything else on the chiplets.

JohnC said that it lowers Kionix's risk to put MEMS on a chiplet. Most companies separate MEMS elements from the compute element and don't try and put them on the same silicon.

Design Costs

Ed was worried about the cost of design rising, and too few foundries working at the leading edge. "Will costs continue to rise or will it follow the same maturation as in the past to get lower for the second-tier guys?"

Wally: As the cost of designs goes up, we always have predictions that hardly anyone will do leading-edge designs. But as we develop experience, costs come down. However, a lot of the costs used to be somewhere else and now get dinged against the chip, so you need to be careful to compare apples to apples. Despite the costs, the amount of money going into fabless startups has soared, with $2B/year just going into AI startups. They are financed well, $10-20M per company, so it's an explosion of new companies. They're all doing high-level synthesis for the datapath. The differentiation is at the C++ level, where you can do simulation a thousand times as fast, and then use high-level synthesis (HLS) to go to implementation.

JohnC: The tools and capabilities are making it more accessible to a wider range of people. AI used to be done with microprocessors but now it's going custom with a big influx of people.

Chong: Tools and capabilities making it more accessible to a wide range of people. AI/ML was done with uP but now it’s going custom. So big influx of people.

Jack: The fundamental trend is specialization versus general purpose:

A GPU from NVIDIA is about 84% inefficient, you pay $5K, I don't even know the price, but if you are Google and deploying millions, you build your own TPU. If you are Cisco, you can't just use a Tomahawk processor from Broadcom, you have to customize the hardware. You can argue it is a necessary evil, but if you are concerned about differentiation, you have no choice. Everyone now has their own chip-development teams since the payback is enormous. Everyone wants their own chips under the ASIC model. It’s an exciting model."

Supply-Chain Security

Ed moved on to one of my favorite topics, security. And in particular, supply-chain security.

Wally: Outside the chip, attention is there. The question is whether the silicon is secure. The challenge is a mix of what you can provide and whether anyone will pay you for it. "You can prove hackability but you can't prove security." There are no metrics. We need a measure that says that what we've done is better than before, but it's still early days. There needs to be a crisis for people to be ready to invest.

JohnK: SEMI has a program using blockchain to keep track of everything. Counterfeits are one problem. Another is that something gets out of spec, but somehow it gets back into the supply chain and gets sold anyway.

Wally: One challenge is that, in the last 10 years, environmental regulations mean that you can't just dispose of a computer. So they get broken up and put back into the grey market. "The people who buy the most in the grey market is the DoD since they are the only people who buy 40-year-old chips and they can't go anywhere else. It may be 30% of the chips they get from the market."

Jack: We just had a board meeting and we announced that we are moving our entire design environment to the cloud at Google. They brought in their head of security who gave a 45-minute presentation. They have a completely closed system. Every device that comes in is scanned with an SEM. They build their own security chips (see my post Google's Titan: How They Stop You Slipping a Bogus Server into Their Datacenter). They check every time they reboot a computer. They have three vessels that lay private cable across the ocean floor. They are now marketing these tools to other supply chain members to control every aspect of their own internal supply chain. That's what it takes.

Wally: FPGA tools never made much money since the cost of failure is low. But it is high for chips and goes up as the square of number of gates so we see the transition from simulation to emulation to FPGA prototyping, and so on. You need to verify a lot of system functionality at near real speeds before going to prototyping. Validation has just as many people as design but doesn’t have the tools. For example, there are thousands of people testing regression suites at Intel and AMD.

JohnK: Factories are less sophisticated than Yahoo serving you an ad. We concluded we need to look much broader, upstream and downstream. We are looking at what we can do with AI today. Nobody will train systems, so there needs to be a natural way to capture human behavior in the factories.

And with that, we were out of time.

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