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Apparently, asking if something is really a thing is really a thing. So, recently, the SOI consortium organized one of their regular symposia and the thing most people in the audience wanted to know is whether FD-SOI is really a thing.
The SOI consortium deals with all things silicon-on-insulator (SOI) and organizes several symposia in different parts of the world each year. For the last few years the focus has been completely on FD-SOI (or sometimes called UTBB-FDSOI). This stands for ultra-thin-body-and-box-fully-depleted-silicon-on-insulator. You can see where the name comes from by looking at the starting wafer-blank and how a transistor is built on top of it. There is an ultra-thin buried oxide (box) on top of the silicon that makes the bulk of the wafer (I guess that counts as a semiconductor play-on-words), and on top of that there is another ultra-thin layer of silicon (the body). The buried oxide is an insulator and the body forms the transistor channels after manufacture. Since the channel area is backed by an insulator, there are no leakage paths that are not well-controlled by the gate, as there are in bulk planar CMOS. FinFET achieves even better control of the channel by having the gate on both sides of it (in fact, the top, too), but it is a lot more expensive to manufacture.
FinFET has something that FD-SOI does not, namely that with the gate on three sides of the channel it has very good control and has higher drive, at the cost of high capacitance and some thermal complications. FD-SOI has its own trick: the silicon below the box (remember, box is just buried oxide) can also be biased, and while this is not enough to turn the transistor on and off, it is enough to make it either higher performance (called forward body bias or FBB) or lower power (called reverse body bias or RBB). With body bias it is possible to get the supply voltage all the way down to 0.4V, which gives both good static (leakage) power (linear with voltage) and good dynamic low power (goes with the square of the voltage as you might remember from high-school physics). It turns out 0.4V is some sort of minimum possible supply voltage, since any lower than that and the transistors switch so slowly that the N and P transistors are both partially on for a long time, and the crowbar current that flows during that period wipes out the gains from decreasing dynamic power.
This technology was originally developed by ST Microelectronics at 28nm. The technology was licensed to Samsung and also to GLOBALFOUNDRIES. For some time there were really no other announcements and it was unclear whether these licensing agreements were real, or just joint marketing exercises. But then Samsung started to make some announcements. GF decided not to go with 28nm but instead do a 22nm version that they called 22FDX.
For more details on this history and background, see my earlier blog Cadence Tool Suite Qualified for 22FDX Reference Flow (which covers a lot of FD-SOI in general, not just 22FDX).
April 2016 FD-SOI Symposium
On April 13, the latest FD-SOI Symposium was held in San Jose. Everyone attending wanted to know more than what the promise of FD-SOI was, they wanted to know whether it was real, when will volume ramp, how many tapeouts, and so on. Engineering, not marketing. There were not just FD-SOI adherents there, there were people from companies that were FinFET only, there were semiconductor analysts, bankers, and more. There were presentations on a wide range of topics but based on wanting to know concrete facts, for me the most interesting looked to be:
In this blog we will look at the first two of these, how FD-SOI stacks up compared to the alternatives. Then tomorrow we'll look at what the two volume manufacturers said. Plus Cadence presented, too, so I'll summarize what we have been doing in both the EDA tool and IP areas.
Dan hasn't said much about FD-SOI since he's been a bit of a skeptic. Yes, he could buy that 28nm FD-SOI cost less to manufacture and had better performance than 28nm bulk. But that was not world-changing. Then GF came out with 22FDX with real differentiated features that also fit perfectly with the requirements for the exploding (at least in terms of hot air) IoT market. When Dan was invited to participate at the symposium he decided that people didn't want to just hear his own opinions and he needed to talk to real users.
So he did a survey. He interviewed people from six chip companies, four IP companies, two EDA companies, and two universities. They were all versed in SOI and its various flavors. About 75% were decision makers and the rest either had strong internal influence or even industry-wide influence. The results completely surprised him.
Almost 75% of respondents were designing with FD-SOI and almost 70% planned to in the future. Not everyone was drinking the Kool-Aid, about 20% said they might use it and about 10% went with "just say no." About 40% preferred to stick with bulk as long as possible and then go to FinFET. So there turned out to be three categories of people:
The #1 reason people were attracted to FD-SOI, from a technical point of view, was unsurprisingly body-bias and power. What Dan figured was undersold was analog (much easier than in FinFET processes), reliability, and stability (great for automotive and other markets requiring high reliability), and the capability to integrate RF on the same die. The #1 reason from a business point of view was time to money: simpler design, avoiding the complexities of FinFET, and product differentiation from everyone using the same FinFET process.
When FD-SOI was just ST and just 28nm, it was not really credible. Processes require an ecosystem of IP, second sources, EDA tool support, and a roadmap. Now FD-SOI has those things with 28 here today, 22 coming soon, and a roadmap to the future. CEA-LETI has demonstrated feasibility down to 7nm.
To wrap up Dan asked whether FD-SOI is disruptive. His answer is no, it is the things that it enables that will be disruptive: IoT, ADAS/self-driving-cars, and other markets that can use the unique features of FD-SOI. He also feels that the story has been underplayed and that FD-SOI has been outmarketed by FinFET, too. The ecosystem needs design (especially using back-bias) to be easier, to do more to publicize the success stories, and drive the volume to drive learning, yield, cost, etc.
With almost 50% of the people who responded to his survey saying that they will design in it, and another 40% saying they might, it is clear that FD-SOI will co-exist with FinFET. Less than half of respondents said they are going to FinFET. Of course, a lot of the volume for FinFET is in a handful of parts for the mobile industry that ships in huge quantities, and that visibility means that it seems the whole world is FinFET. It is not.
Will Abbey of ARM did something I've not seen before. Almost always comparative data on 28 FD-SOI or even 22FDX compares the performance to 28nm planar. Fewer masks! Lower power! Higher performance! Back bias! However, what everyone wants to know is how does it compare to FinFET. Will had some graphs. "One advantage of running a 400 person organization", he said, "is that you can find a few people for a skunk works project." He presented the results with the preamble that nobody from either ARM or GF had ever seen them before.
The skunk works had been told to analyze how good GF's 22FDX process was compared to LN14LPP, which is Samsung's/GF's 14nm FinFET process. Will had lots of graphs, here are a couple.
The above graph shows power analysis of a block buried deep in one of the ARM® Cortex® processors (I think this is the successor to the A72 that has been sort of pre-announced under the name Artemis with no details yet). This is the uTLB (TLB normally stands for "translation lookaside buffer," which is a critical part of virtual memory translation holding the most recent values on the assumption that they are about to occur again almost immediately). The blue lines show 22FDX at various back bias voltages. The red lines are FinFET, both at 0.8V supply voltages.The big dots below the line show what can be achieved with selective back biasing.
The above graph shows FinFET (red) and FDX with no back-bias (top blue line) or with 1V back-bias (low blue line). The lower line is 50% lower power.
Will's final conclusions:
The presentations, at least those that the respective companies have allowed to be released, are all here.
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