Front-end Design Summit

Wednesday was the annual Front-end Design Summit at Cadence headquarters. This focuses on the digital front-end design tools, which means synthesis, test, and power. Almost any semiconductor seminar has power as one of the main themes. Five or ten years ago everything was about timing but now power signoff is the bigger issue, silicon is so fast and implementation tools so good that power and area are rarely the gating issue to tapeout. Not to say we wouldn't all like more performance and smaller area, but more performance mostly only comes with more power anyway.

Paul Cunningham, Cadence's VP of R&D for front-end design (the second English Paul who studied computer science at Cambridge University, me being the first) gave an overview of the whole product line and how it has evolved over the last couple of years. Cadence has transformed their tools with common engines and an architecture that scales to use large numbers of cores to cope with huge designs. These are the tools that end with the letters US (except for Joules, where somehow an LE slipped in between the U and the S). This combination means that very large designs can be distributed over lots of compute power and the common engines ensure very high accuracy.

Genus Synthesis Solution is the new synthesis product announced just before DAC earlier this year. Joules RTL Power Solution is the new RTL power analysis product, which actually contains a sort of stripped down version of the Genus solution under the hood. It is not possible to estimate power accurately at the RTL level without good estimates of interconnect, clock distribution, and more. If there was a theme of the day it was definitely power.

Later in the day, Steve Carlson of Cadence gave a summary of how all this new technology can be used to move power estimation earlier in the design process. Power, like several other aspects of design, suffers from the fact that early in the design cycle when architectural changes are possible, there is limited accuracy, whereas late in the design cycle during signoff, where there is as much accuracy as you want, there is very little that can be done. The number is what it is. RTL seems to be a sweet spot as it is, largely, for verification. Digital design is largely about getting the RTL right and then using tools that are largely automatic to reduce that to actual silicon structures.I especially liked his cautionary tale about a company that designed an eight-core version of their product after seeing speedups with two and four cores. But the thermal issues were not correctly handled and so it ran barely faster than the single-core version. That's an expensive mistake. Getting system power right early in the design cycle is really, really important. With the risk of thermal runaway, chips can't ignore these issues until signoff. Power affects thermal which affects power, which affects performance.

Later still in the day, Cadence's Jay Roy went into much more detail about how the Joules solution works, how accurate it is, and how it can be used in a system context.

At the end of the day there was a panel session on...power. Technically it was called "Closing the Power Gap for Wearable Devices Through Early System-level Design". I moderated it and the panel was Leah Clark of Broadcom, Fred Jen of Qualcomm, Anthony Hill of Texas Instruments, and Jay Roy of Cadence. We did talk somewhat about wearables but also touched on whether IoT devices are going to be largely analog rather than digital, which process nodes they might be in, whether anything interesting is happening in battery technology. Quite a bit on what processing should be done locally in the device, versus up in the cloud or in your phone. Security seems like a challenge since the encryption technologies we have available are anything but low power. If there was any conclusion it was that big A small d mixed-signal design is still really hard and stuff falls into the cracks between SPICE and static timing analysis, for example.

If there was a second theme of the day it was manufacturing test. Test time is a huge challenge. Test has been transformed over the last decade as scan test and BIST have become ubiquitous and test compression technologies help to get the test time and test pin count down. Mun Sing Loh of Lattice Semiconductor talked about low pin count compression solutions (earlier in the day he talked about their first experiences using Genus Synthesis Solution at Lattice). Mike Vachon of Cadence gave an update on the latest test solution in Encounter Test.

If you attended the summit (I think perhaps even if you registered and didn't manage to make it), then the presentations will all be posted soon and you will get an email with a link.

Next week, on December 10th, is the Implementation Summit, focused around the Innovus Implementation System and the suite of US signoff tools. Information and registration is here. I'll see you there.