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A lot of constraints in datacenters are fixed even though others are increasing. Networking bandwidth is doubling every two years. However, faceplate density is fixed, so there needs to be more bandwidth per socket and lower power for a given bandwidth. Within the datacenter it is all about power efficiency. Over longer distances, between datacenters, everything is driven by spectral efficiency, how much bandwidth can we get down each fiber. The cloud is also changing everything as more and more workloads are deployed into the cloud. Traditional datacenters are growing at around 5% (and probably slowing) whereas cloud datacenters are growing at 33% CAGR.
The above graph shows the explosive growth of datacom and telecom optical tranceivers, and the fast transition from 10G to 100G over the next couple of years. The whole ecosystem is supply limited, and increases in supply chain efficiency are necessary to meet the demand ramp in the above graph. This is where the efficiency of high volume silicon processing and packaging comes in.
By the way, people often use the words "baud" and "bits per second" interchangeably (baud is named after Émile Baudot). But technically the baud-rate is the rate at which the signal is sampled. It is only the same as the bit rate if every sample contains one bit. Early Ethernet used Manchester encoding where a 0 followed by a 1 represented 0, and a 1 followed by a 0 represented 1, so that there was a signal transition in the middle of every bit for clock recovery, and so the baud rate was twice the bps (10 Mbps in the original Blue Book Ethernet). Now, technologies like PAM4 transmit two bits on each sample, so the baud-rate is half the bps.
Last April, GLOBALFOUNDRIES (GF) announced their roadmap for on-chip photonic elements.At the recent Linley Cloud Hardware Conference, Ted Letavic, a senior fellow, presented more details. The above diagram shows the roadmap. Phase 1 is complete and we are in phase 2. In the Q&A at the end I asked what the significance of 200mm vs 300mm was because Ted emphasized that 300mm produced better optics, with lower wave-guide loss and higher bandwidth. He said that it wasn't the size of the wafer so much as the fact that 200mm equipment is older and has less tight overlay registration.
The technology GF is using has germanium photodectors (for the receiver) and interferometer modulators (for the transmit path). All functions except the light source are integrated into the silicon foundry flow. A few numbers for these components:
Transmit: PAM4 with 50Gbps data rate over at 25Gbaud line rate, with a BER < 10-12 without FEC, ER of 6dB
Receive: 28.5 Gbaud, 400mV peak-peak extracted eye, BER <-12 with 58uA p-p sensitivity, 0.7A/W photodetector sensitivity
On-chip waveguides: insertion loss is 2-3X lower with 300mm vs 200mm, SiPh direct-detect reduces optical loss by 2-3dB
One challenge with silicon photonics is how to connect the on-die silicon photonics to the fiber itself. This can turn out to be the most expensive part of manufacture. Alignment of the fiber can be most of the cost of the module.
The GF approach is to use a selective mask and etch to form a deep V-groove on each die. The fiber is then inserted into the groove, thus automatically aligning it with the optical mode converters. There is no fixture to align. In fact, the die does not even need to be powered up during fiber insertion, unlike alignment-based approaches. See the diagram below. Ted said that this approach is in production and currently shipping into the telecom industry.
The diagram below shows the whole package including the fiber attach. There are 3 die on a thru-silicon-via interposer onto the package laminate. The plan in the future is to eventually go to a 3D option where the fibers can be attached anywhere onto the die, not just at the edge.
Ted thinks that the packaging and fiber attach is likely to be the bottleneck to the ramp I showed at the start of this post. He thinks that passive fiber attach can really help grow the business. It is critical since you can't design a photonic die without the packaging, so keeping packaging simple is crucial.
During the Q&A, Ted was asked about test. He said that testability needs to be built in. The majority of the electrical test is done at the wafer level. Of course final test has to be done after fiber attach.
If you want to design your own chip for GF to manufacture, the Cadence PDKs are available from GF.
I wrote a post Silicon Photonics that was an introduction to the area based on Gilles Lamant's presentation. The transition is happening very fast, driven by photonic solutions having 2-5X higher interconnect power efficiency, and better signal integrity. But to me the game-changer is the direct fiber attach that gets semiconductor HVM efficiencies into the whole manufacturing process.
Nothing to do with Ted's presentation, but GF also recently announced some major capacity expansion. Here are the highlights: