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The 2018 Turing Award, informally the Nobel prize in Computer Science, has been awarded to Dave Patterson and John Hennessy (along wth a cool $1M). They invented the RISC, the Reduced Instruction Set Computer. John Hennessy with MIPS at Stanford, and Dave Patterson with RISC (usually known as RISC-I these days) at UC Berkeley. They also wrote many versions of the standard textbook on computer architecture called Computer Architecture: A Quantitative Approach. The picture below shows the original 1990 edition of the book, along with the 1990 edition of the professors.
In his keynote at the Shanghai RISC-V Workshop last year, Dave Patterson related how several things came together to give him the idea of RISC.
The first hint came from IBM. They had built a chip, the 801, with a simple architecture, in some ways the first RISC. It was a research chip, and not intended for commercial exploitation. John Cocke had developed a compiler for it, and to keep the compiler simple, it assumed that the processor only had register-register operations except for a single load and a single store instruction. As an experiment, the compiler was re-targeted to the IBM 360, which had a rich instruction set with all sorts of complicated instructions, and a whole portfolio of operations that combined registers with memory (such as adding the contents of a memory location to a register). Due to the architecture of the compiler, the re-targeted compiler could only use the register-register instructions of the IBM 360, along with a load and a store. To everyone's surprise, the code that it produced ran three times faster than the code produced by the regular compiler using the entire instruction set.
The second hint came from Digital Equipment (DEC) where Patterson, still an untenured associate professor, was on sabattical. There he found out that DEC had discovered that 20% of the instructions required 60% of the microcode—but only accounted for 0.2% of the execution time.
The third hint also came from Digital. Based on experience, he knew that the microprocessor designers would basically copy the mainframe designers, and use lots of microcode. But microcode bugs were always being discovered, and so mainframes like the Vax needed field-upgradable microcode. They would need to find a way to have field-upgradable microprocessors. Being an academic, he wrote a paper about it. The paper was rejected.
However, rejected paper in hand, Dave realized he was still right: If they imitated the mainframe people and built complex microcoded instruction sets, then they would need to be fixable.
Plus, from the two earlier hints above, microcode wasn't looking so good anyway.
Dave realized that the solution to all of this was to get rid of microcode. Microcode had originally been motivated by performance differences between ROM and ferrite-core RAM that were no longer true anyway. In the silicon world, the tradeoffs were different. Instead of having microcode, just run code directly out of a fast on-chip instruction cache, and stick to simple instructions, have a simple pipeline, and get the entire processor onto a single chip so that there was no need to deal with signals that crossed chip boundaries.
Being a professor back in Berkeley, he had slaves aka grad students. In 1982, students built the first RISC chip. It was 45,000 transistors. The RISC II, which was a better design, was in 3um NMOS, ran at 3MHz, and the size was 60 mm2.
Victory was total.
In fact, even the most ubiquitous CISC of them all, the Intel x86 instruction set, is implemented as a RISC. The first thing the instruction decode does is to turn complex instructions into RISC instructions, and then these are scheduled into multiple execution units.
Another dead end was VLIW, at least for general-purpose computing. There are just too many unused resources (the approach seems to work well for DSPs—Tensilica is a VLIW architecture). Intel's Itanium was a VLIW architecture, which is all you need to know. AMD actually designed the 64-bit extension of x86 while Intel was going down the Itanium dead end. So we have the odd situation today that huge cloud datacenters run enormous amounts of computing. Intel supplies someting like 95+% of the chips—but they all run an AMD instruction set architecture.
Over at Stanford, Hennessey and his group came up with the MIPS architecture. One insight that they had was that it was good to put all the complexity in the compiler to keep the architecture and the silicon implementation simple.
This approach of having a very simple architecture that could be implemented on a single chip, and a powerful compiler to exploit it, is how all subsequent instruction set architectures have been designed. The Arm ISA, the Power architecture, and, of course, RISC-V all adhere to this philosophy.
One of the people in that MIPS group was Chris Rowen, who would go on to found Tensilica, which was acquired by Cadence a few years ago. Hennessy was Chris's PhD supervisor.
It turns out that I have written, at least indirectly, about both professors already.
At the RISC-V Workshop in Shanghai last year, Dave Patterson gave the keynote 50 Years of Computer Architecture:
Fifty Years of Computer Architecture: The First 20 Years
Fifty Years of Computer Architecture: The Last 30 Years
I also covered the two of them in passing in a post about a lunch I had with Chris Rowen (who was one of the founders of MIPS with Hennessy and others):
Are General-Purpose Microprocessors Over?
On the right is Dave Patterson today (well, in Shanghai last year), with the current edition of their undergraduate textbook Computer Organization and Design. The legacy of Dave's work has been carried on by Krste Asańovic and the creation of the RISC-V ISA.
John went on to be President of Stanford from 2008 to 2016.
Both professors have retired. But the gravitational attraction in Mountain View is too strong. Dave works at Google, and John was recently announced as executive chairman of Alphabet, Google's parent company (so I guess John is sort of Dave's boss these days).
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