Get email delivery of the Cadence blog featured here
At HOT CHIPS last week, one of the themes that ran through several of the presentations, including both keynotes by AMD and TSMC, was that optimal system design requires using chiplets and 3D packaging technology. A couple of the presenters used the word "chipletifying" to describe doing design this way, so if it becomes a word in common currency (at least in our industry) then you read it here first.
The big drivers for this are:
I pulled this out of the AMD presentation on Zen2 but I could have taken something similar from other presentations.
Zen2 was covered by Dan Bouvier and David Suggs of AMD, and also by Lisa Su, AMD's CEO, in her keynote. I'm not going to go into all the details, since it is not all that new now. I still think it is remarkable that they managed to improve their instructions per cycle by 15% at this point. It's either a huge achievement or else their IPC was non-competitive before.
But for this post, it is all about their chiplets, which can be configured to address the desktop market ("Matisse" is next-generation Ryzen) and server market ("Rome" is next-generation Epyc).
Andrew Yang of Intel presented the Spring Crest SoC (also known as the Nervana NNP-T). It is on an interposer with the main SoC surrounded by four HBM memories.
The second-day keynote was by TSMC's Philip Wong. I will cover it in detail in a post of its own next week. But here is one picture from his presentation.
Rangharajan Venkatesan of NVIDIA presented their research project using network-on-chip (NoC) and network-on-package (NoP) chiplet integration strategy.
Patrick Knebel of HP Enterprise presented their Gen-Z chipset. This involves three chiplets that are built on the same reticle, but are then combined in different combinations on interposers to create the optical-to-electrical bridge, the optical switch, and the electrical-to-optical switch, all with integrated optics.
Sticking with optical integration, Ayar Labs presented their TeraPHY, which they call a chiplet technology for low-power, high-bandwidth, in-package optical I/O.
Sanjeev Khushu and Wilfred Gomes of Intel presented Lakefield: Hybrid Cores in a 3D Package. This uses the 3D packaging technology that Intel calls foveros, which they revealed earlier this year.
I think I probably missed a couple of other examples that were very similar to these examples (adding HBM to a processor core, for example). I put a short note about each of these just to show how widespread using these More than Moore packaging technologies has become. I would say that there has been a big change in the last 12 months, at least for these high-end CPUs and GPUs.
Of course, that's not the only way to scale. Cerebras went in the other direction with a wafer-scale processor. See my post from last week HOT CHIPS: The Biggest Chip in the World.
Common themes in these chips were:
I think that this is a trend that we are going to continue to see a lot more of going forward, with a progression from adding memory, towards stacked logic die. One challenge that Philip Wong pointed out in his keynote, is that there are no tools for doing 3D design once you get beyond the simplest cases.
Sign up for Sunday Brunch, the weekly Breakfast Bytes email.