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I slipped into an obscure bar in the no-man's-land between Santana Row and downtown San Jose. It was a weekday afternoon. There was only one other person in the bar.
"I'm from imec," he said.
"Ssh," I said. "Walls have ears."
"imec's not a secret. We're in a town called Leuven outside Brussels. Everyone knows that."
"I thought it was Louvain."
"You don't want to go there. Belgian politics. Flemish and French speakers...let's just say they differ in more than language. Belgium didn't even have a government for nearly two years a few years ago. Nobody could agree on anything."
"Well, however you pronounce Leuven, people don't realize that Belgium is the center of advanced semiconductor research. We like to pretend it's Silicon Valley."
He laughed. "The only silicon in Silicon Valley is in the name. We engage with all the leading-edge guys."
"But all that leading-edge stuff is secret."
"Not at imec. We operate out in the pre-competitive timeframe."
"So 5 nanometer?"
"No, that's all competitive now. We did 5nm a couple of years ago. We're looking at 3nm. We just taped out a 3nm testchip with Cadence."
"So reports of the death of scaling are premature, it seems."
"Well, it's getting harder to do."
"You just reduce the contacted-poly-pitch and the metal pitch and you're done. Moore's Law's been going for 50 years."
"It's not so simple anymore. We can't reduce the CPP at all. It's sticking at 42nm. Just the metal scales. It'll be 21nm, down from 32nm. But that only gives us a one-third reduction, and we want a half. We need to use some other tricks."
"Like what?" I asked.
"We just presented a joint paper, Cadence and imec, at SPIE."
"Spy? That's something I know about."
"No, not 'spy'. S - P - I - E. It's the society of...lithography."
"How do you get lithography out of 'PIE'?"
"I forget. Anyway, this paper. It's called Track Height Reduction: How Low Can You Go?"
"Like limbo dancing?"
"I suppose. But it's really about the fact that for 3nm we need to do aggressive DTCO."
"DTCO?" I asked. "Is that a secret organization? Like the NSA?"
"No. It's Design Technology Co-Optimization. We need to put some things in the process to let us make the standard cell libraries smaller. Scaling boosters, we call them."
"How do you do that? In one direction, standard cells are simply what they are based on the transistor pitch. In the other, it's the metal pitch."
"True. So the only way is to cut some metal tracks out. At 7nm and 5nm, we had 6.5 tracks. Or 5 MINT tracks?"
"Mint? Like peppermint?"
"No. The MEOL interconnect. Middle-end-of-line."
"How do you have an end in the middle?"
"Yeah, makes no sense. But that's what we call it anyway. So there are 5 MINT tracks and 1.5 tracks of power and ground."
"How do you fit power and ground into 1.5 tracks? That's two signals in the space of 1.5."
"The cells get flipped on alternating rows. So they share power and ground with the next row. But they are double-width metal, so it's 1.5 instead of 1. But it also means we have to use EUV."
"Wow. Is that the weird thing where you spray, like, thousands of drops of tin, and zap them with a death ray. And they explode in a flash of light?"
He looked at me and realized it would take too long to explain. "Something like that," he said.
"So what about for 3nm? For this Cadence testchip. How many tracks did you use?"
"We go down to 5.5 tracks. 4 MINT tracks."
"That sounds tight."
"It is. Especially in the middle of the cell. We'll need an SDC for M0A to make it work."
"Synopsys Design Constraints?" I was proud of myself for knowing what SDC stands for.
"No. I don't even know what that means. I'm a process guy. Spacer-Defined Cut."
"Oh," I said. Apparently I just know enough to be dangerous.
"But we want to go tighter. Just 4.5 tracks. 3 MINT."
"But...is there even room for the transistors?"
"Not if we stick to two-fin transistors. We need to go down to a single fin."
"A single fin? Is there enough drive? Won't the performance suffer?"
"You're right. So we're looking at stacked nanosheets. A type of gate-all-around."
"GAA. I've heard of that. Silicon nanowires."
"Yes. Except we use flattened oval wires instead of circular ones. That's why they're called nanosheets."
"No. We can use the same cell architecture. But underneath the metal, there is the new structure. There are three nanosheets per transistor instead of the old two fins. More drive, less space."
"Tastes great, less filling."
He looked disparagingly at me. "Be serious. These are next-generation transistors, not light beers. Anyway, if anything it's too filling."
"What do you mean?"
"The center track of the cell is the handshaking track for P to N connection. So we need to extend M0A all the way to the middle of the cell."
He pulled out some colored markers and drew a quick sketch on the back of a beer mat.
"See these tight staggered and irregular cuts. It will need special processing." He ringed the relevant areas with a red pen.
"You want all the details? Okay. We do the metal contact to source and drain before we do the replacement metal gate. We do the contacts separately. We do the N contacts first. We need two patterns, one deep and one shallow. We need to use a replacement spacer scheme to ensure dielectric isolation at the tip of the contact extension. Then we do the same thing after for the P contacts."
I had no idea what he was talking about, but I was too proud to admit it. I'm in...well, I'd better not say. My employer likes to keep things secret.
"So what about pin access? For the router." I know that this is the big EDA issue with small standard cells. You can manufacture them, but the router can't get in there.
"It's tricky. If you look at just a single cell, it looks like there are enough metal resources for pickup. But when you place the same cell down multiple times, there really aren't, and that leads to congestion. Cells like that will need to be redesigned to make the ports more accessible. Plus we'll need supervias."
"What's a via when it's super?"
"It goes up more than one level. From metal to poly, skipping the MINT layers. But there's a better way than just redesigning the cells. Double height cells."
"So two rows, I guess."
"Exactly. Want to see some layout?"
Before I could answer, he pulled out a sheet of paper printed with a couple of cells.
"See on the left, that's a double height cell. You can go further. This one on the right is triple height."
My Apple watch beeped. "Well, I need to get going," I said.
"Here," he said, pulling out another sheet of paper. "It summarizes everything in one place. On the left is 7nm. To get to 5nm...or what the foundries call 5nm but imec confusingly calls iN7...we got 35% from pitch scaling and then the other 15% from adding the contact over active gate, with the SAGC, the self-aligned gate contact. To go to 3nm, we get 35% from scaling again, but SAGC was a one-time thing so we need to get the other 15% from scaling boosters like supervias, and cutting a track out of the cells. But if we go to smaller transistors, it looks like we can cut out a second track, for another 15%."
I folded the paper and put it in my jacket pocket. My eyes were nearly blinded as I stepped out of the dark bar into the California sunshine.
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