HPSC: RISC-V in Space

NASA needs a new computer. Being NASA, of course, this has an acronym, HPSC. Unusually for NASA, this has four letters, not three. Remember back in the Apollo program (assuming you were born) when we all knew what TLI, LEM, and all the rest stood for? HPSC stands for High Performance Space Computer. The plan is that in the future, everything that NASA and JPL (NASA Jet Propulsion Laboratory in Pasadena, CA) will be HPSC-based, but there is also an expectation that it will have commercial applications such as in aviation. Space missions are largely autonomous, and that requires computer power. Lots of it. Very early on, it was decided that the new HPSC would use RISC-V for its ISA, not something proprietary or something NASA/JPL created themselves. In fact, I think it most unlikely that anyone will ever again define an ISA that is not RISC-V based.

Of course, NASA has been involved in putting computers in space for a long time. For example, see my post about the Apollo Guidance Computer (yeah, the three-letter acronym AGC) The First Computer on the Moon.

At the recent RISC-V Summit in December, Pete Fiacco presented HPSC – Radically Advancing the Capabilities of Space-Based Computing. Pete is a member of the HPSC leadership team, a JPL consultant, and Managing Partner of Executive Technology Consulting.

HPSC has to go into space (well, duh!), which means, in particular, it requires radiation tolerance. We have to worry about that in modern chips here on earth since we live on a radioactive planet bombarded with cosmic rays. But the earth's magnetic field and the atmosphere largely protect us. In space, neither of those is true. There are other major requirements, but here are two. Nobody is going to be making service calls on a vehicle once it has left. Yes, we did it once, to fix the Hubble Telescope, but that was just in low earth orbit, and we had a space shuttle. So that means that there is a requirement for fault tolerance. Security is another foundational critical capability. There is a saying in automotive that there is "no safety without security," and that is double so in space. Nobody is really all that interested in your car, but that is not true of any high-profile space mission, so if a hacker or a foreign adversary can take gain control, it doesn't matter how radiation tolerant or how fault tolerant your computer is.

Pete presented a nice hierarchy of needs. At the top are the requirements for commercial smartphone processors, namely performance per watt and use of industry standards. For high-end desktop processors (or server processors for that matter), you can add high-speed interfaces and hardware-supported time and space partitioning. But that is not enough for HPSC space compute. You need to add in the big three I already mentioned, fault tolerance, radiation hardening, and complete security.

You can see the difference between your smartphone and a Mars rover, just to pick a couple of examples. If your smartphone gets hit by a high-energy particle and needs to be rebooted, it's not that big of a deal. If it totally fails, you are annoyed. Maybe it's insured, but worst case, you are out the $1,000 it takes to buy a new one. If a Mars rover needs to be rebooted, that is probably no big deal, part of fault tolerance. But if it fails completely, the Mission fails too. Even JPL probably doesn't have a spare, and even if it did, getting it to Mars is a zillion dollars and a few years.

So, the HPSC Prime Directive is to deliver unique computing capabilities for high-performance, fault-tolerant, secure systems in space and on earth.

To summarize HPSC, it is a multi-core RISC-V SoC with:

• Fault-tolerant, functional safety
• Software-defined functionality
• Extensible from a single chip to a multi-chip supercomputer, with possible capabilities for AI/ML and vector processing
• Industry standards for interfaces, operating systems, software stacks
• Extremely high performance per watt
• Complete platform security through the manufacturing life cycle and from hardware up to user data

Of course, the HPSC is more than a chip or a family of chips. It needs boards, a software stack, and all the additional capabilities that make a processor a complete product.

The main partner in all this is Microchip, who had actually presented a little about this project in its keynote the day before. Microchip, in turn, is partnered with SiFive since it uses a SiFive processor as the basis for HPSC.

I mentioned autonomy as a requirement earlier. If you look at the above diagram, it looks identical to what you might find from any autonomous vehicle company's PowerPoint. Well, except for orbital orientation — your car and you are in trouble if it is off the ground. I used to have a Mazda Miata, and one of the things I did was to add a roll bar. I now have a Mini convertible, and it has a sort of explosive roll bar, a bit like an airbag. When the safety system detects a problem, such as a potential rollover, it detonates squibs beneath two rods hidden behind the rear seats, which then lock into place. If the vehicle does roll over, then the occupants are protected. So yes, even my car has a sort of orbital orientation system in its computers.

So what does HPSC actually look like? What are its capabilities? Well, you can see from the above diagram (the format of which seems to be copied from any number of Apple keynotes describing its own chips).

However, there is more than just Microchip involved. There is an entire ecosystem of SBCs, software (both commercial and OSS), and so forth. Plus, the SpaceVPX bus. If you want to do a deeper dive into VPX, you can read the SpaceVPX Interoperability Assessment. It probably goes deeper than you want to go since it is nearly 100 pages long.

In conclusion, as Pete put it:

HPSC redefines what is possible for the future of space exploration

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