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I was DesignCon recently. It is a bit of a weird conference, since it covers a wide range of topics, and the exhibition is even weirder—ranging from $200,000 oscilloscopes, to Cadence IP and signal integrity tools, to people selling specialized gold coaxial connectors. It turns out that what today is DesignCon used to be called SuperCon, and was a high-speed connector conference. Today, the focus is more on PCB and signal integrity, covering test and measuring equipment, boards, software and more—but there are still remnants of its heritage in the various vendors selling connectors, cables and other hardware.
Cadence was there. We focused on four areas:
Cadence had a paper accepted to the conference itself called Team-Based PCB PDN Design Methodology Enabled by IC Target Impedance Constraints. It was authored by Brad Brim, Sam Chitwood, Suomin Cui, Chuanlin Lv and Hongjun Bo, all of Cadence. Most of the presentation was by Brad and Sam.
The problem that they were addressing was this. Power delivery networks (the PDN of the title) require matching to the SoC. Traditionally, this has been done in a very prescriptive manner, giving details of exactly what decoupling capacitors (decaps) are required and where. These are predicated on a particular PCB stackup. The problem with this approach is that it makes it very hard for the system designers to push the performance higher or reduce the cost since the data needed to work with is not available. Further, when more than one SoC is on the same board, the two manufacturers may have made different stackup requirements making it impossible to stick within both sets of guidelines, and risking that vendors will simply say that they the design is non-compliant if anything goes wrong. Large customers can push some of the work back onto the IC vendors to simulate and approve the design, but this creates a lot of additional work when different customers all require signoff. The only way the IC vendor can avoid this work would be to give full details of the chip internals to the system group using the chip, but that is never going to happen for obvious confidentiality reasons. There are plenty of other challenges too, ranging from schematics spanning dozens of pages, arbitrary net names, non-intuitive layout and more.
Target impedance is becoming the preferred method for IC vendors to specify system-level AC PDN design requirements. This allows PCB designs to choose freely their own stackup and decoupling solution as long as it meets the specified targets. These targets can either be specified at the package/board interface or else at the die/package interface along with a package model.
Target impedance as the communication vehicle raises two immediate questions:
The basic issue with calculating the target impedance is that most IC simulation tools operate in the time domain and produce waveforms that represent the current demands of the die. But for PCB design, a frequency domain approach is required and, in turn, this means that the IC tools current waveforms be converted into target impedance. This requires converting complex multi-die parasitic models into simpler net-based lumped L-R models that are equivalent. The paper describes this in more detail exactly how to do this.
Having got the target impedance specifications, a very different AC PDN methodology can be used. The engineers can make choices about stackup and PDN plane placement, and guide the placement of decaps during schematic generation. Again, there is too much detail to simply put in a blog post, the paper has all the details.
This approach enables a team-based methodology whereby information now available in the schematic can be leveraged throughout the design cycle. Schematic and layout designers can run AC PDN impedance checking simulations with pass/fail results. This can be done early in the design cycle instead of building up problems for the power integrity (PI) engineer to discover later when there is less time to address them and which typically leads to last-minute fire drills.