IEDM 2017

The start of December means it is the International Electron Devices Meeting in San Francisco (it used to be in Washington alternate years but it is in San Francisco for the forseeable future). I have been here all week. Highlights were keynotes from AMD and TSMC, largely about packaging. Major announcements of Intel's 10nm process, and GLOBALFOUNDRIES' 7nm process (despite the difference in names, these are roughly equivalent process nodes). On the first morning, Gordon Moore was honored as an EDS Celebrated Member. Of course, I hoped he'd be here in person, as he had been at many IEDM meetings over the years, but he sent a video from his house in Hawaii.

There is usually a theme running through IEDM and if I had to summarize this years meeting, it would be that we kinda sorta know what we are doing down to 5nm, then it is almost certainly going to be gate all around (GAA) silicon nanosheets. To keep on a reasonable process cadence (with a small "c"), we will need to use design technology co-optimization (DTCO) as well as an aggressive use of advanced 3D packaging technologies. On the memory side, vertical flash will continue, DRAM is struggling and nobody knows what comes next, and some of the MRAM technologies are starting to be significant.

Tutorials

The Saturday of IEDM consists of tutorials. I wasn't able to attend that day, but as a member of the press I get given all the materials. When I have some time, I'll take a look through and see if I can distill the day into some interesting lessons. The tutorials were:

• The Evolution of Transistors towards Low Power and High Performance IoT Applications, by Dae Won Ha of Samsung
• Hardware Opportunities in Cognitive Computing, Near- and Far-Term, by Geoffrey Burr of IBM
• Silicon Photonics for Next-Generation Optical Interconnects, by Joris Van Campenhout of imec
• Negative Capacitance Transistors, by Sayeef Salahuddin of UC Berkeley
• Fundamental, Thermal, and Energy Limits of PCM and ReRAM, Eric Pop of Stanford
• 2.5D Interposers and High Density Fan Out Packaging as Enablers for Future Systems Integration, by Venkatesh Sundaram of Georgia Tech

Short Courses

Sunday is taken up by two all-day short courses that run in parallel, one on logic and one on memory. I attended the logic one, which was titled Boosting Performance, Ensuring Reliability, Managing Variation in Sub-5nm CMOS. I will cover this in a post of its own. Just to whet your appetite, the presentations were by technologists from IBM, Applied Materials, imec, Intel, GLOBALFOUNDRIES, and TechInsight.

Plenary Session

Monday, the conference itself kicked off with the plenary session. But before that are awards. I won't list them all. I knew from the handouts that Gordon Moore was being honored, and I hoped he would be there in person, but he accepted the award from Hawaii by a pre-recorded video. At an age of 88, flying a ten hour round trip to get yet another award after a distinguished career probably isn't that appealing.

There were three keynotes. 

• Lisa Su, AMD's CEO (and a device physicist by background) kicked off IEDM proper with a presentation on Multi-Chip Technologies to Unleash Computing Performance Gains over the Next Decade.
• Next, Adrian Ionescu of the Nanolab at Ecole Polytechnique de Fédérale de Lausanne (EPFL) on Energy Efficient Computing and Sensing in the Zettabyte Era: from Silicon to the Cloud.
• Finally, Jack Sun of TSMC on System Scaling for Intelligent Ubiquitous Computing.

I will write about these sessions later in their own post.

3D Integration and Packaging

After lunch, there was a focus session on 3D integration and packaging. It was packed with great info. There were lots of details on Sony's 3-layer CMOS image sensor (in the space of 2 layers), integrating all the voltage regulation (including the inductors) into the package, replacing packages and PCBs with glass substrate, new packaging technologies from foundries, and building cube computers with liquid coolant pumping through channels between the die. I'll cover that in a separate post.

Twenty Years of Copper

Exactly twenty years ago, at IEDM 1997, IBM and Motorola surprised everyone by (separately) announcing copper BEOL for 0.22um (or 220nm as we would call it today). The two processes were developed independently, but the two companies were cooperating on PowerPC in those days so needed compatible processes. The picture below shows the timeline from the invention of the damascene process, to gettting copper interconnect going, and a look to the future.

The current version at GF is the 12^th generation copper back end. On a typical server chip, there are 17 levels of coper wiring, totally a staggering 30-50 miles of interconnect. When people say that the interconnect on a chip is finer than a human hair, they are correct. But, in fact, that is so far off as to be comical. The interconnect is 1/7000 the width of a human hair, and 1/30 the size of those 0.22um wires 20 years ago.

The motivation for adoption was originally:

• performance increase of 10-20%
• cost reduction (eventually)
• copper wires are 500 times more reliable than aluminum (that was the big element at the beginning)
• extendability (Al would have lasted at most a couple more generations)

There are four high conductivity metals: silver, copper, gold and aluminum. All require cladding of some sort. Silver has very high solubility in glass, IBM's insulator, so that would have been unworkable. So copper was the best choice. Early on they demonstrated Cu better than Al for line resistance, via resistance, line capacitance, electro-migration and stress migration (there was no thinning at all at first). Almost as big a challenge was that they avoided Cu poisoning of the devices (or the whole fab!). Every manufacturer needs special protocols as to how to handle copper. Originally it was regarded as too bad of a contaminant to let anywhere near a fab.

IBM divulged some of what they were doing, in particular the electroplating. But not the TaN/alpha-Ta barrier. Looking back, it is clear that they had a big lead in manufacturing for years. The barrier information was only published 7 years later.

Looking to the future, the following paper was by IBM (along with partners GF and Samsung) on copper fully-aligned via. A via aligned in both directions (so that the via is the intersection of Mx, Mx+1 and Vx) is regarded as essential to continue copper for 7nm and beyond. Intel, for example, are switching to cobalt.

Intel and GLOBALFOUNDRIES

IEDM got smart and put three of the biggest draws on Wednesday, to ensure that the last day of the conference wasn't half empty. The morning session opened with Intel announcing details of their 10nm process. The morning ended with GLOBALFOUNDRIES announcing details of their 7nm process. Despite the different headline numbers, these are basically the same process generation. I also got to sit down for an hour with Gary Patton, ex-IBM and now CTO of GLOBALFOUNDRIES. I will cover that too.

That was followed by a second plenary session where Nobel Laureate Hiroshi Amano presented Development of a Sustainable Smart Society based on Transformative Electronics. He won the Nobel prize for physics in 2014 (along with others) for "the invention of efficient blue light-emitting diodes which has enabled bright and energy-saving white light sources". I will cover that with the other keynotes.

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