IEDM and RISC-V Summit 2022 Previews

There are two big events coming up in the first couple of weeks of December. IEDM is in San Francisco from December 3-7 (the conference proper starts on the 5th, with tutorials and short courses at the weekend. See below for more details). The following week is the RISC-V Summit in San Jose from December 13-14 (with tutorials on the 15th).

In previous years, these ended up in the same week, which meant I found myself driving up and down from San Francisco to San Jose depending on which parts I really needed to attend. But I suspect I'm about the only person in the world who goes to both events: IEDM is about the lowest-level transistor structures, and RISC-V is about instruction sets and microprocessors. Nobody is really interested in both, but I cover both for Breakfast Bytes. Then, in January, I'll go up another level and cover what everyone calls the Consumer Electronics Show but is actually just its initials, CES.

Let's dig a little deeper. But if you just want to attend, skip to the end of this post where there are links for registration to both events.

IEDM

IEDM is held in the San Francisco Hilton on O'Farrell Street (just near Union Square). I think the hotel was formed out of three separate hotels, requiring weird things like escalators with just half-a-dozen steps. It's the only hotel I've stayed in where I've found myself having to go down to the lobby, cross it, and then come back up, since I couldn't find my way around the floor I was already on. The event will be held in person from December 3-7, and on demand from December 12.

IEDM is the International Electron Devices Meeting. Today, it is mostly about various forms of transistors and integrated circuit structures. But when IEDM started, nearly 70 years ago, it was all about vacuum tubes, with a little section at the end for those weird transistor thingies that nobody was really interested in.

As always, IEDM optionally starts on Saturday afternoon with tutorials. This year they are:

• Device Innovations to Extend CMOS Scaling for the 2nm Node and Beyond, Tenko Yamashita, IBM
• Sensors for IoT, Automobile, Health and Other, Carlotta Guiducci, EPFL
• Resistive Memories-Based Concepts for Neuromorphic Computing, Elisa Vianello, CEA-Leti
• The Era of Advanced Packaging and Hybrid Bonding, Sitaram Arkalgud, Tokyo Electron Ltd.
• FEOL Reliability: from Essentials to Advanced and Emerging Devices and Circuits, Ben Kaczer, Imec
• Fabrication and Three-Dimensional Integration Technologies, Qiangfei Xia, University of Massachusetts

Then, on Sunday, there are two short courses that run in parallel. One is always memory-oriented and one is logic-oriented. This year they are:

• High-Performance Technologies for Datacenter and Graphics to Enable Zetta-Scale Computing, organized by Ruth Brain, Intel
• Next-Generation High-Speed Memory, organized by Yih Wang, TSMC

On Monday, the conference proper kicks off with a plenary session, starting at 9:00am. The three plenary speakers are:

• Anne Kelleher, Executive Vice President/General Manager of Technology Development, Intel: Celebrating 75 years of transistor innovation by looking ahead to the next set of industry grand challenges
• Yusuke Oike, General Manager, Sony Semiconductor Solutions: Expanding Human Potential through Imaging and Sensing Technologies
• Maud Vinet, Quantum Hardware Program Manager, CEA-Leti: Enabling full fault-tolerant quantum computing with silicon-based VLSI technologies

After that, for the rest of the three days, there are about a dozen parallel tracks. As always, there are some special focus sessions. This year they are:

• Advanced Heterogeneous Integration: Chiplets and System-in-Packaging
• DNA Digital Data Storage, Transistor-Based DNA Sequencing, and Bio-Computing
• Emerging Implantable-Device Technology
• Quantum Information and Sensing
• Special Topics in Non-Von Neumann Computing

For fuil details, click on the IEDM banner above (or here).

RISC-V

The event will be held in person in the San Jose Convention Center from December 13-14 (with tutorials on December 15).

I'm not going to list all the sessions here. I'll put all the keynotes (although some are still to be announced). Also, presentations by people of particular note in the RISC-V community, such as the creators of the ISA, or just things that caught my eye.

Tuesday 9:00am: Calista Redmond, Chairman RISC-V International: Welcome and Opening Remarks

Tuesday 9:20am: Keynote to be announced

Tuesday 9:40am: Lip-Bu Tan keynote. Until the end of last year, Cadence's CEO, of course. Now Chairman, Walden International Founding Managing Partner, Celesta Capital, and Walden Catalyst Ventures; Executive Chairman, Cadence Design Systems

Tuesday 10:00am: Simon Davidmann, my old colleague from Ambit days...a long time ago. Now Chair of OpenHW Group Verification Task Group, Imperas Software: RISC-V Spotlight: Improving RISC-V Quality with Verification Standards and Advanced Methodologies

Tuesday 11:40am: Krste Asanović, one of the fathers of the RISC-V ISA and a professor at UC Berkeley (plus positions at SiFive and Chair of RISC-V International): The Future of AI with RISC-V.  But what caught my eye was "The presentation will include a walk-on with a major US hyperscaler, to be named later, who will show how RISC-V is being integrated into datacenter applications and explain the reasons for their choice." It is always interesting when hyperscalers use something other than x86.

Tuesday 11:40am (so in parallel with Krste above): Mark Himelstein, the CTO of RISC-V International: The Road Ahead

Tuesday 2:15pm: John Davis, Barcelona Supercomputing Center (the most beautiful supercomputing center in the world in the former Chapel Torre Girona) Is RISC-V HPC? RISC-V is HPC!

Tuesday 4:45pm: Dave Ditzel, CTO of Esperanto. I wrote about their chip in my post HOT CHIPS: Esperanto's Dave Ditzel and 1000 Minions: Real World Results Using Thousands of RISC-V Cores for AI and Beyond

Wednesday 9:00am: Krste Asanović keynote, title TBD

Wednesday 9:20am: Keynote to be announced

Wednesday 9:45am: Pete Fiacco keynote, Member HPSC Leadership Team, JPL Consultant, Managing Partner, Executive Technology Consulting: 

Wednesday 10:45am: Zvonimir Bandic of Cadence, Improving RISC-V Commercial Adoption

For full details, see the RISC-V Summit webpage.

Registration

 

Also, although you can't yet register, the call for contributions to CadenceLIVE Silicon Valley is now open. Plus, mark your calendar to save the date.

 

Sign up for Sunday Brunch, the weekly Breakfast Bytes email.

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